Small volume laboratory on a chip measurements incorporating the quartz crystal microbalance to measure the viscosity-density product of room temperature ionic liquids

A microfluidic glass chip system incorporating a quartz crystal microbalance (QCM) to measure the square root of the viscosity-density product of room temperature ionic liquids (RTILs) is presented. The QCM covers a central recess on a glass chip, with a seal formed by tightly clamping from above outside the sensing region. The change in resonant frequency of the QCM allows for the determination of the square root viscosity-density product of RTILs to a limit of similar to 10 kg m(-2) s(-0.5). This method has reduced the sample size needed for characterization from 1.5 ml to only 30 mu l and allows the measurement to be made in an enclosed system.

Low SNR Capacity for MIMO Rician and Rayleigh-Product Fading Channels with Single Co-channel Interferer and Noise

This paper studies the ergodic capacity of multiple-input multiple-output (MIMO) systems with a single co-channel interferer in the low signal-to-noise-ratio (SNR) regime. Two MIMO models namely Rician and Rayleigh-product channels are investigated. Exact analytical expressions for the minimum energy per information bit, Eb/N0min, and wideband slope, S0, are derived for both channels. Our results show that the minimum energy per information bit is the same for both channels while their wideband slopes differ significantly. Further, the impact of the numbers of transmit and receive antennas, the Rician K factor, the channel mean matrix and the interference-to-noise-ratio (INR) on the capacity, is addressed. Results indicate that interference degrades the capacity by increasing the required minimum energy per information bit and reducing the wideband slope. Simulation results validate our analytical results.

SoC memory hierarchy derivation from dataflow graphs

Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation and how these memory architectures can be mapped to a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and by creating memory hierarchies, off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm, with a minimal increase in memory size. This analysis is verified using results gathered from implementation of the motion estimation algorithm on a Xilinx Virtex-4 FPGA, where the delay between the memories and processing elements drops from 14.2 ns down to 1.878 ns through the refinement of the memory architecture. Care must be taken when modeling these algorithms however, as inefficiencies in these models can be easily translated into overuse of hardware resources.