Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

Helical resonator filters with improved power handling capabilities for space applications

The power-handling capabilities of helical resonator filters for space applications are discussed. Emerging difficulties due to the multipaction effects are highlighted. A method is proposed to increase specified power handling without significantly sacrificing the size/quality factor. Experimental verification is attained by means of a fabricated prototype for which measured filter response and multipaction test results are obtained and presented.

Analysis and Design of Class-E3F and Transmission-Line Class-E3F2 Power Amplifiers

In this paper, analysis and synthesis approach for two new variants within the Class-EF power amplifier (PA) family is elaborated. These amplifiers are classified here as Class-E3 F2 and transmission-line (TL) Class-E3 F 2. The proposed circuits offer means to alleviate some of the major issues faced by existing topologies such as substantial power losses due to the parasitic resistance of the large inductor in the Class-EF load network and deviation from ideal Class-EF operation due to the effect of device output inductance at high frequencies. Both lumped-element and transmission-line load networks for the Class-E 3 F PA are described. The load networks of the Class-E3 F and TL Class-E 3 F2amplifier topologies developed in this paper simultaneously satisfy the Class-EF optimum impedance requirements at fundamental frequency, second, and third harmonics as well as simultaneously providing matching to the circuit optimum load resistance for any prescribed system load resistance. Optimum circuit component values are analytically derived and validated by harmonic balance simulations. Trade-offs between circuit figures of merit and component values with some practical limitations being considered are discussed. © 2010 IEEE.

Power Stored and Quality Factors in Frequency Selective Surfaces at THz Frequencies

A study of the external, loaded and unloaded quality factors for frequency selective surfaces (FSSs) is presented. The study is focused on THz frequencies between 5 and 30 THz, where ohmic losses arising from the conductors become important. The influence of material properties, such as metal thickness, conductivity dispersion and surface roughness, is investigated. An equivalent circuit that models the FSS in the presence of ohmic losses is introduced and validated by means of full-wave results. Using both full-wave methods as well as a circuit model, the reactive energy stored in the vicinity of the FSS at resonance upon plane-wave incidence is presented. By studying a doubly periodic array of aluminium strips, it is revealed that the reactive power stored at resonance increases rapidly with increasing periodicity. Moreover, it is demonstrated that arrays with larger periodicity-and therefore less metallisation per unit area-exhibit stronger thermal absorption. Despite this absorption, arrays with higher periodicities produce higher unloaded quality factors. Finally, experimental results of a fabricated prototype operating at 14 THz are presented.

Protection Assessment using Reduced Power System Fault Data

Wavelet transforms provide basis functions for time-frequency analysis and have properties that are particularly useful for the compression of analogue point on wave transient and disturbance power system signals. This paper evaluates the compression properties of the discrete wavelet transform using actual power system data. The results presented in the paper indicate that reduction ratios up to 10:1 with acceptable distortion are achievable. The paper discusses the application of the reduction method for expedient fault analysis and protection assessment.

Transmission-Line Class-E Power Amplifier With Extended Maximum Operating Frequency

A novel Class-E power amplifier (PA) topology with transmission-line load network is presented in this brief. When compared with the classic Class-E topology, the new circuit can increase the maximum operating frequency up to 50% higher without trading the other Class-E figures of merit. Neither quarterwave line/massive radio-frequency choke for collector/drain biasing nor additional fundamental-frequency output matching circuit are needed in the proposed PA, thus resulting in a compact design. Closed-form formulations are derived and verified by simulations with practical design limitations carefully taken into consideration and good agreement achieved.

Prediction-Based Power-Performance Adaptation of Multithreaded Scientific Codes

Computing has recently reached an inflection point with the introduction of multicore processors. On-chip thread-level parallelism is doubling approximately every other year. Concurrency lends itself naturally to allowing a program to trade performance for power savings by regulating the number of active cores; however, in several domains, users are unwilling to sacrifice performance to save power. We present a prediction model for identifying energy-efficient operating points of concurrency in well-tuned multithreaded scientific applications and a runtime system that uses live program analysis to optimize applications dynamically. We describe a dynamic phase-aware performance prediction model that combines multivariate regression techniques with runtime analysis of data collected from hardware event counters to locate optimal operating points of concurrency. Using our model, we develop a prediction-driven phase-aware runtime optimization scheme that throttles concurrency so that power consumption can be reduced and performance can be set at the knee of the scalability curve of each program phase. The use of prediction reduces the overhead of searching the optimization space while achieving near-optimal performance and power savings. A thorough evaluation of our approach shows a reduction in power consumption of 10.8 percent, simultaneous with an improvement in performance of 17.9 percent, resulting in energy savings of 26.7 percent.

Dynamic global security-aware synthesis using System-C

A dynamic global security-aware synthesis flow using the SystemC language is presented. SystemC security models are first specified at the system or behavioural level using a library of SystemC behavioural descriptions which provide for the reuse and extension of security modules. At the core of the system is incorporated a global security-aware scheduling algorithm which allows for scheduling to a mixture of components of varying security level. The output from the scheduler is translated into annotated nets which are subsequently passed to allocation, optimisation and mapping tools for mapping into circuits. The synthesised circuits incorporate asynchronous secure power-balanced and fault-protected components. Results show that the approach offers robust implementations and efficient security/area trade-offs leading to significant improvements in turnover.

Randomized caches for power-efficiency

Embedded processors are used in numerous devices executing dedicated applications. This setting makes it worthwhile to optimize the processor to the application it executes, in order to increase its power-efficiency. This paper proposes to enhance direct mapped data caches with automatically tuned randomized set index functions to achieve that goal. We show how randomization functions can be automatically generated and compare them to traditional set-associative caches in terms of performance and energy consumption. A 16 kB randomized direct mapped cache consumes 22% less energy than a 2-way set-associative cache, while it is less than 3% slower. When the randomization function is made configurable (i.e., it can be adapted to the program), the additional reduction of conflicts outweighs the added complexity of the hardware, provided there is a sufficient amount of conflict misses.

Amplitude-modulation characteristics of power-combining Class-E amplifier with finite choke

Power back-off performances of a new variant power-combining Class-E amplifier under different amplitude-modulation schemes such as continuous wave (CW), envelope elimination and restoration (EER), envelope tracking (ET) and outphasing are for the first time investigated in this study. Finite DC-feed inductances rather than massive RF chokes as used in the classic single-ended Class-E power amplifier (PA) resulted from the approximate yet effective frequency-domain circuit analysis provide the wherewithal to increase modulation bandwidth up to 80% higher than the classic single-ended Class-E PA. This increased modulation bandwidth is required for the linearity improvement in the EER/ET transmitters. The modified output load network of the power-combining Class-E amplifier adopting three-harmonic terminations technique relaxes the design specifications for the additional filtering block typically required at the output stage of the transmitter chain. Qualitative agreements between simulation and measurement results for all four schemes were achieved where the ET technique was proven superior to the other schemes. When the PA is used within the ET scheme, an increase of average drain efficiency of as high as 40% with respect to the CW excitation was obtained for a multi-carrier input signal with 12 dB peak-to-average power ratio. © 2011 The Institution of Engineering and Technology.

Strong electronic correlation in the hydrogen chain: A variational Monte Carlo study

In this paper, we report a fully ab initio variational Monte Carlo study of the linear and periodic chain of hydrogen atoms, a prototype system providing the simplest example of strong electronic correlation in low dimensions. In particular, we prove that numerical accuracy comparable to that of benchmark density-matrix renormalization-group calculations can be achieved by using a highly correlated Jastrow-antisymmetrized geminal power variational wave function. Furthermore, by using the so-called "modern theory of polarization" and by studying the spin-spin and dimer-dimer correlations functions, we have characterized in detail the crossover between the weakly and strongly correlated regimes of this atomic chain. Our results show that variational Monte Carlo provides an accurate and flexible alternative to highly correlated methods of quantum chemistry which, at variance with these methods, can be also applied to a strongly correlated solid in low dimensions close to a crossover or a phase transition.