Compact Toffoli gate using weighted graph states

We introduce three compact graph states that can be used to perform a measurement-based Toffoli gate. Given a weighted graph of six, seven, or eight qubits, we show that success probabilities of 1/4, 1/2, and 1, respectively, can be achieved. Our study puts a measurement-based version of this important quantum logic gate within the reach of current experiments. As the graphs are setup independent, they could be realized in a variety of systems, including linear optics and ion traps.

Equalisation of time variant multipath channels using amplitude banded LMS algorithms

For the purpose of equalisation of rapidly time variant multipath channels, we derive a novel adaptive algorithm, the amplitude banded LMS (ABLMS); which implements a nonlinear adaptation based on a coefficient matrix. Then we develop the: ABLMS algorithm as the adaptation procedure for a linear transversal equaliser (LTE) and a decision feedback equaliser (DFE) where a parallel adaptation scheme is deployed. Computer simulations demonstrate that with a small increase of computational complexity, the ABLMS based parallel equalisers provide a significant improvement related to the conventional LMS DFE and the LMS LTE in the case of a second order Markov communication channel model.

Noise resilience and entanglement evolution in two nonequivalent classes of quantum algorithms

The speedup provided by quantum algorithms with respect to their classical counterparts is at the origin of scientific interest in quantum computation. However, the fundamental reasons for such a speedup are not yet completely understood and deserve further attention. In this context, the classical simulation of quantum algorithms is a useful tool that can help us in gaining insight. Starting from the study of general conditions for classical simulation, we highlight several important differences between two nonequivalent classes of quantum algorithms. We investigate their performance under realistic conditions by quantitatively studying their resilience with respect to static noise. This latter refers to errors affecting the initial preparation of the register used to run an algorithm. We also compare the evolution of the entanglement involved in the different computational processes.

Analysis of Receiver Algorithms for LTE SC-FDMA Based Uplink MIMO Systems

This letter derives mathematical expressions for the received signal-to-interference-plus-noise ratio (SINR) of uplink Single Carrier (SC) Frequency Division Multiple Access (FDMA) multiuser MIMO systems. An improved frequency domain receiver algorithm is derived for the studied systems, and is shown to be significantly superior to the conventional linear MMSE based receiver in terms of SINR and bit error rate (BER) performance.

Revealing differences in gene network inference algorithms on the network level by ensemble methods

Motivation: The inference of regulatory networks from large-scale expression data holds great promise because of the potentially causal interpretation of these networks. However, due to the difficulty to establish reliable methods based on observational data there is so far only incomplete knowledge about possibilities and limitations of such inference methods in this context.

Results: In this article, we conduct a statistical analysis investigating differences and similarities of four network inference algorithms, ARACNE, CLR, MRNET and RN, with respect to local network-based measures. We employ ensemble methods allowing to assess the inferability down to the level of individual edges. Our analysis reveals the bias of these inference methods with respect to the inference of various network components and, hence, provides guidance in the interpretation of inferred regulatory networks from expression data. Further, as application we predict the total number of regulatory interactions in human B cells and hypothesize about the role of Myc and its targets regarding molecular information processing.

SoC memory hierarchy derivation from dataflow graphs

Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation and how these memory architectures can be mapped to a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and by creating memory hierarchies, off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm, with a minimal increase in memory size. This analysis is verified using results gathered from implementation of the motion estimation algorithm on a Xilinx Virtex-4 FPGA, where the delay between the memories and processing elements drops from 14.2 ns down to 1.878 ns through the refinement of the memory architecture. Care must be taken when modeling these algorithms however, as inefficiencies in these models can be easily translated into overuse of hardware resources.