Idealised operation of zero-voltage-switching series-L/parallel-tuned Class-E power amplifier

An analysis of a modified series-L/parallel-tuned Class-E power amplifier is presented, which includes the effects that a shunt capacitance placed across the switching device will have on Class-E behaviour. In the original series L/parallel-tuned topology in which the output transistor capacitance is not inherently included in the circuit, zero-current switching (ZCS) and zero-current derivative switching (ZCDS) conditions should be applied to obtain optimum Class-E operation. On the other hand, when the output transistor capacitance is incorporated in the circuit, i.e. in the modified series-L/parallel-tuned topology, the ZCS and ZCDS would not give optimum operation and therefore zero-voltage-switching (ZVS) and zero-voltage-derivative switching (ZVDS) conditions should be applied instead. In the modified series-L/parallel-tuned Class-E configuration, the output-device inductance and the output-device output capacitance, both of which can significantly affect the amplifier's performance at microwave frequencies, furnish part, if not all, of the series inductance L and the shunt capacitance COUT, respectively. Further, when compared with the classic shunt-C/series-tuned topology, the proposed Class-E configuration offers some advantages in terms of 44% higher maximum operating frequency (fMAX) and 4% higher power-output capability (PMAX). As in the classic topology, the fMAX of the proposed amplifier circuit is reached when the output-device output capacitance furnishes all of the capacitance COUT, for a given combination of frequency, output power and DC supply voltage. It is also shown that numerical simulations agree well with theoretical predictions.

Inverse Class E amplifier and oscillator phase noise characteristics

This paper gives the first experimental characterisation of the phase noise response of the recently introduced Inverse Class E topology when operated as an amplifier and then as an oscillator. The results indicate that in amplifier and oscillator modes of operation conversion efficiencies of 64%, and 42% respectively are available, and that the excess PM noise added as a consequence of saturated Class E operation results in about a 10 dB increase in PM over that expected from a small-signal Class A amplifier operating at much lower efficiency. Inverse Class E phase transfer dependence on device drain bias and flicker noise are presented in order to show, respectively, that the Inverse Class E amplifier and oscillator follow the trends predicted by conventional phase noise theory. © 2007 EuMA.

Balanced class e amplifier based multimode modulator

In this paper we present an adaptation to the classical I/Q modulator topology which simultaneously allows it to operate both as a multi-modulation standard modulator, and as a high efficiency balanced amplifier. This is made possible by concurrently exploiting the ability of the Class E amplifiers to produce variable output power at maximum power added efficiency, PAE, by simple dc bias control while faithfully reproducing phase encoded signals. Experimental evidence for the behaviour of the modulator when operated in QPSK mode at 2.33 GHz with a 1 Msymbol/s rate shows that Error Vector Magnitude of less than 5% with amplifier PAE of 65% is possible. The multimode modulator presented here should lead to significantly reduced complexity, enhanced functionality transceivers for use in dc power sensitive handheld wireless applications. © 2007 EuMA.

Exploring figures of merit associated with the suboptimum operation of class-E power amplifiers

Closed-form design equations for the operation of a class-E amplifier for zero switch voltage slope and arbitrary duty cycle are derived. This approach allows an additional degree of freedom in the design of class-E amplifiers which are normally designed for 50 duty ratio. The analysis developed permits the selection of non-unique solutions where amplifier efficiency is theoretically 100 but power output capability is less than that the 50 duty ratio case would permit. To facilitate comparison between 50 (optimal) and non-50 (suboptimal) duty ratio cases, each important amplifier parameter is normalised to its corresponding optimum operation value. It is shown that by choosing a non-50 suboptimal solution, the operating frequency of a class-E amplifier can be extended. In addition, it is shown that by operating the amplifier in the suboptimal regime, other amplifier parameters, for example, transistor output capacitance or peak switch voltage, can be included along with the standard specification criteria of output power, DC supply voltage and operating frequency as additional input design specifications. Suboptimum class-E operation may have potential advantages for monolithic microwave integrated circuit realisation as lower inductance values (lower series resistance, higher self-resonance frequency, less area) may be required when compared with the results obtained for optimal class-E amplifier synthesis. The theoretical analysis conducted here was verified by harmonic balance simulation, with excellent agreement between both methods. © The Institution of Engineering and Technology 2007.

Even order harmonic Series-L/Parallel-Tuned Class-E frequency multiplier

In this brief, we propose a new Class-E frequency multiplier based on the recently introduced Series-L/Parallel-Tuned Class-E amplifier. The proposed circuit produces even-order output harmonics. Unlike previously reported solutions the proposed circuit can operate under 50% duty ratio which minimizes the conduction losses. The circuit also offers the possibility for increased maximum operating frequency, reduced peak switch voltage, higher load resistance and inherent bond wire absorption; all potentially useful in monolithic microwave integrated circuit implementations. In addition, the circuit topology suggested large transistors with high output capacitances can be deployed. Theoretical design equations are given and the predictions made using these are shown to agree with harmonic balance circuit simulation results.

Design strategies for dual-band class-e power amplifier using composite right/left-handed transmission lines

In this article we propose a technique for dual-band Class-E power amplifier design using composite right/left-handed transmission lines, CRLH TLs. Design equations are presented and design procedures are elaborated. Because of the nonlinear phase dispersion characteristic of CRLH TLs, the single previous attempt at applying this method to dual bond Class-E amplifier design was not sufficient to simultaneously satisfy, the minimum requirement of Class-E impedances at both the fundamental and the second harmonic frequencies. This article rectifies this situation. A design example illustrating the synthesis procedure for a 0.5W-5V dual band Class-E amplifier circuit simultaneously operated at 900 MHz and 2.4 GHz is given and compared with ADS simulation.

Inverse Class-E Amplifier With Transmission-Line Harmonic Suppression

This paper reports on the design methodology and experimental characterization of the inverse Class-E power amplifier. A demonstration amplifier with excellent second and third harmonic-suppression levels has been designed, constructed, and measured. The circuit fabricated using a 1.2-min gate-width GaAs MESFET is shown to be able to deliver 22-dBm output power at 2.3 GHz. The amplifier achieves a peak power-added efficiency of 64 % and drain efficiency of 69 %, and exhibits 11.6 dB power gain when operated from a 3-V supply voltage. Comparisons of simulated and measured results are given with good agreement between them being obtained. Experimental results are presented for the amplifier's response to Gaussian minimum shift keying modulation, where a peak error vector modulation value of 0.6% is measured.

2.4 GHz Class-E power amplifier with transmissionline harmonic terminations

The design procedure, fabrication and measurement of a Class-E power amplifier with excellent second- and third-harmonic suppression levels are presented. A simplified design technique offering compact physical layout is proposed. With a 1.2 mm gate-width GaAs MESFET as a switching device, the amplifier is capable of delivering 19.2 dBm output power at 2.41 GHz, achieves peak PAE of 60% and drain efficiency of 69%, and exhibits 9 dB power gain when operated from a 3 V DC supply voltage. When compared to the classical Class-E two-harmonic termination amplifier, the Class-E amplifier employing three-harmonic terminations has more than 10% higher drain efficiency and 23 dB better third-harmonic suppression level. Experimental results are presented and good agreement with simulation is obtained. Further, to verify the practical implementation in communication systems, the Bluetooth-standard GFSK modulated signal is applied to both two- and three-harmonic amplifiers. The measured RMS FSK deviation error and RMS magnitude error were, for the three-harmonic case, 1.01 kHz and 0.122%, respectively, and, for the two-harmonic case, 1.09 kHz and 0.133%. © 2007 The Institution of Engineering and Technology.

Sensitivity characteristics of inverse Class-E power amplifier

In this paper, an analysis is performed in order to determine the effects that variations in circuit component values, frequency, and duty cycle have on the performance of the newly introduced inverse Class-E amplifier. Analysis of the inverse Class-E amplifier under the generalized condition of arbitrary duty cycle is performed and it is shown that the inverse Class-E amplifier is reasonably tolerant to circuit parameter variations. When compared to the conventional Class-E amplifier the inverse Class-E amplifier offers the potential for high efficiency at increased output power as well as higher peak output power levels than are available with a conventional Class-E amplifier. Further the inverse Class-E amplifier provides more flexibility for deployment with a pulsewidth modulator as the means of producing full-carrier amplitude modulation (AM) due to its ability to operate to high AM modulation indices.

Transmission line matching effects on the performance of shunt-C/series-tuned and series-L/parallel-tuned Class-E amplifiers

The impact that the transmission-line load-network has on the performance of the recently introduced series-L/parallel-tuned Class-E amplifier and the classic shunt-C/series-tuned configuration when compared to optimally derived lumped load networks is discussed. In addition an improved load topology which facilitates harmonic suppression of up to 5 order as required for maximum Class-E efficiency as well as load resistance transformation and a design procedure involving the use of Kuroda's identity and Richard's transformation enable a distributed synthesis process which dispenses with the need for iterative tuning as previously required in order to achieve optimum Class-E operation. © 2005 IEEE.

Analysis of the effect of finite d.c. blocking capacitance and finite d.c. feed inductance on the performance of inverse class-E amplifiers

The first analysis and synthesis equations for the newly introduced inverse Class-E amplifier when operated with a finite d.c. blocking capacitance and a finite d.c.-feed inductance are presented in the paper. Closed-form design equations are derived in order to establish the circuit component values required for optimum synthesis. Excellent agreement between numerical simulation results and theoretical prediction is obtained. It is shown that drain efficiency approaching 100 at a pre-specified output power level can be achieved as zero-current switching and zero-current derivative conditions are simultaneously satisfied. The proposed analysis offers the prospect for realistic MMIC implementation.