124 resultados para PHASED-ARRAY


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A novel most significant digit first CORDIC architecture is presented that is suitable for the VLSI design of systolic array processor cells for performing QR decomposition. This is based on an on-line CORDIC algorithm with a constant scale factor and a latency independent of the wordlength. This has been derived through the extension of previously published CORDIC algorithms. It is shown that simplifying the calculation of convergence bounds also greatly simplifies the derivation of suitable VLSI architectures. Design studies, based on a 0.35-µ CMOS standard cell process, indicate that 20 such QR processor cells operating at rates suitable for radar beamfoming can be readily accommodated on a single chip.

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In this article, we present position indication functionality as obtained by using a retrodirective array, thereby allowing location information extraction of the position of the remote transmitter with which the retrodirective array is cooperating. This is carried out using straightforward circuitry with no requirement for complex angle of arrival algorithms, thereby giving a result in real time enabling tracking of fast moving transmitters. We show using a 10 x element retrodirective array, operating at 2.4 GHz that accuracies of far-field angle of arrival of within +/- 1 degrees over the arrays +/- 30 degrees azimuth field of view are possible. While in the near-field for angles of arrival of +/- 10 degrees it is possible to extract the position of a dipole source down to a resolution of 032 lambda. (C) 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1031-1034, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25097

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In this paper, we provide experimental evidence to show that enhanced bit error rate (BER) performance is possible using a retrodirective array operating in a dynamically varying multipath environment. The operation of such a system will be compared to that obtained by a conventional nonretrodirective array. The ability of the array to recover amplitude shift keyed encoded data transmitted from a remote location whose position is not known a priori is described. In addition, its ability to retransmit data inserted at the retrodirective array back to a spatially remote beacon location whose position is also not known beforehand is also demonstrated. Comparison with an equivalent conventional fixed beam antenna array utilizing an identical radiating aperture arrangement to that of the retrodirective array are given. These show that the retrodirective array can effectively exploit the presence of time varying multipath in order to give significant reductions in BER over what can be otherwise achieved. Additionally, the retrodirective system is shown to be able to deliver low BER regardless of whether line of sight is present or absent.

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We investigate the situation where there are obstructing elements present in the near field of a retrodirective array. We describe three scattering cases, (1) by an array of straight wires, (2) by low loss medium density fibre board partially obscuring the array, and (3) by concrete blocks, totally and then partially obscuring the array. For all scenarios retrodirective action was shown to be able to provide various degrees of automatic compensation for loss in gain relative to that which would have occurred for a conventional (non-retrodirective) array in the presence of the same scattering screens. Gain improvements of up to 10 dB were observed when the retrodirective array was used. In addition we show how the induced variation of received and re-transmited amplitudes across the array, caused by the scattering screens, is the principle mechanism causing deterioration of the retrodirective arrays monostatic response.

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The spatial dynamics of the optical emission from an array of 50x50 individual microplasma devices is reported. The array is operated in noble gas at atmospheric pressure with an ac voltage. The optical emission is analyzed with phase and space resolution. It has been found that the emission is not continuous over the entire ac period, it occurs only twice in each cycle. Each of the observed emission phases shows a self-pulsing of the discharge, with several bursts of emission of a fixed width and repetition rate. Cross-talk between the individual devices can be observed through spatially resolved measurements. (C) 2008 American Institute of Physics.

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Acute promyelocytic leukemia (APL) is associated with a reciprocal and balanced translocation involving the retinoic acid receptor-alpha (RARalpha). All-trans retinoic acid (ATRA) is used to treat APL and is a potent morphogen that regulates HOX gene expression in embryogenesis and organogenesis. HOX genes are also involved in hematopoiesis and leukemogenesis. Thirty-nine mammalian HOX genes have been identified and classified into 13 paralogous groups clustered on 4 chromosomes. They encode a complex net-Work of transcription regulatory proteins whose precise targets remain poorly understood. The overall function of the network appears to be dictated by gene dosage. To investigate the mechanisms involved in HOX gene regulation in hematopoiesis and leukemogenesis by precise measurement of individual HOX genes, a small-array real-time HOX (SMART-HOX) quantitative polymerase chain reaction (PCR) platform was designed and validated. Application of SMART-HOX to 16 APL bone marrow samples revealed a global down-regulation of 26 HOX genes compared with normal controls. HOX gene expression was also altered during differentiation induced by ATRA in the PML-RARalpha(+) NB4 cell line. PML-RARalpha, fusion proteins have been reported to act as part of a repressor complex during myelold cell differentiation, and a model linking HOX gene expression to this PML-RARalpha repressor complex is now proposed.

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A three-step one pot reaction/purification protocol was developed to facilitate rapid access to benzimidazole-based nucleosides, for which benzoylated benzimidazoribosyl nucleosides incorporating boronic esters were key reaction intermediates.

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Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

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The most promising way to maintain reliable data transfer across the rapidly fluctuating channels used by next generation multiple-input multiple-output communications schemes is to exploit run-time variable modulation and antenna configurations. This demands that the baseband signal processing architectures employed in the communications terminals must provide low cost and high performance with runtime reconfigurability. We present a softcore-processor based solution to this issue, and show for the first time, that such programmable architectures can enable real-time data operation for cutting-edge standards
such as 802.11n; furthermore, by exploiting deep processing pipelines and interleaved task execution, the cost and performance of these architectures is shown to be on a par with traditional dedicated circuit based solutions. We believe this to be the first such programmable architecture to achieve this, and the combination of implementation efficiency and programmability makes this implementation style the most promising approach for hosting such dynamic architectures.