Platform-Independent IP Transmission over Wireless Networks: The WINE Approach

First demonstration of a working dynamically configurable architecture for wireless IP networks. The programmable architecture was as result of a European collaboration between Industry and University and was applied to a range of IP wireless networks. The work laid the foundations for subsequent research initiatives (including the UK) into programmable wireless networks as well as influencing future wireless standards (e.g. ITU-T).EU project WINE (Wireless Internet NEtworking), -1999-10028.

WFI Optimised PWGPS for Wireless IP Networks

The paper describes the design and analysis of a packet scheduler intended to operate over wireless channels with spatially selective error bursts. A particularly innovative aspect in the design is the optimization of the scheduler algorithm to minimize the worst-case fairness index (WFI) for real-time IP traffic.

Demographic Change, Social Security Systems, and Savings

Abstract In theory, improvements in healthy life expectancy should generate increases in the average age of retirement, with little effect on savings rates. In many countries, however, retirement incentives in social security programs prevent retirement ages from keeping pace with changes in life expectancy, leading to an increased need for life-cycle savings. Analyzing a cross-country panel of macroeconomic data, we find that increased longevity raises aggregate savings rates in countries with universal pension coverage and retirement incentives, though the effect disappears in countries with pay-as-you-go systems and high replacement rates.

Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

Packet classification by multi-level cutting of the classification space: An algorithmic-architectural solution for IP packet classification in next generation networks

Traditionally, the Internet provides only a “best-effort” service, treating all packets going to the same destination equally. However, providing differentiated services for different users based on their quality requirements is increasingly becoming a demanding issue. For this, routers need to have the capability to distinguish and isolate traffic belonging to different flows. This ability to determine the flow each packet belongs to is called packet classification. Technology vendors are reluctant to support algorithmic solutions for classification due to their non-deterministic performance. Although CAMs are favoured by technology vendors due to their deterministic high lookup rates, they suffer from the problems of high power dissipation and high silicon cost. This paper provides a new algorithmic-architectural solution for packet classification that mixes CAMs with algorithms based on multi-level cutting the classification space into smaller spaces. The provided solution utilizes the geometrical distribution of rules in the classification space. It provides the deterministic performance of CAMs, support for dynamic updates, and added flexibility for system designers.