38 resultados para Bi-Multiplication


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The Bi-directional Evolutionary Structural Optimisation (BESO) method is a numerical topology optimisation method developed for use in finite element analysis. This paper presents a particular application of the BESO method to optimise the energy absorbing capability of metallic structures. The optimisation objective is to evolve a structural geometry of minimum mass while ensuring that the kinetic energy of an impacting projectile is reduced to a level which prevents perforation. Individual elements in a finite element mesh are deleted when a prescribed damage criterion is exceeded. An energy absorbing structure subjected to projectile impact will fail once the level of damage results in a critical perforation size. It is therefore necessary to constrain an optimisation algorithm from producing such candidate solutions. An algorithm to detect perforation was implemented within a BESO framework which incorporated a ductile material damage model.

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Since a key requirement of known life forms is available water (water activity; aw), recent searches for signatures of past life in terrestrial and extraterrestrial environments have targeted places known to have contained significant quantities of biologically available water. However, early life on Earth inhabited high-salt environments, suggesting an ability to withstand low water-activity. The lower limit of water activity that enables cell division appears to be ∼ 0.605 which, until now, was only known to be exhibited by a single eukaryote, the sugar-tolerant, fungal xerophile Xeromyces bisporus. The first forms of life on Earth were, though, prokaryotic. Recent evidence now indicates that some halophilic Archaea and Bacteria have water-activity limits more or less equal to those of X. bisporus. We discuss water activity in relation to the limits of Earth's present-day biosphere; the possibility of microbial multiplication by utilizing water from thin, aqueous films or non-liquid sources; whether prokaryotes were the first organisms able to multiply close to the 0.605-aw limit; and whether extraterrestrial aqueous milieux of ≥ 0.605 aw can resemble fertile microbial habitats found on Earth.

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The overall aim of the work presented in this paper has been to develop Montgomery modular multiplication architectures suitable for implementation on modern reconfigurable hardware. Accordingly, novel high-radix systolic array Montgomery multiplier designs are presented, as we believe that the inherent regular structure and absence of global interconnect associated with these, make them well-suited for implementation on modern FPGAs. Unlike previous approaches, each processing element (PE) comprises both an adder and a multiplier. The inclusion of a multiplier in the PE means that the need to pre-compute or store any multiples of the operands is avoided. This also allows very high-radix implementations to be realised, further reducing the amount of clock cycles per modular multiplication, while still maintaining a competitive critical delay. For demonstrative purposes, 512-bit and 1024-bit FPGA implementations using radices of 2(8) and 2(16) are presented. The subsequent throughput rates are the fastest reported to date.

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Tetrahexahedral Pd nanocrystals (THH Pd NCs) were prepared on a glassy carbon electrode using a programmed square-wave potential electrodeposition method, and modified by Bi adatoms with a range of coverages via the cyclic voltammetry method. The reactivity of the catalysts prepared towards ethanol electrooxidation reaction (EOR) was studied in alkaline medium at various temperatures and under other conditions that practical fuel cells operate. Significant activity enhancements were observed for the Bi-modified THH Pd NCs with an optimum Bi coverage (θBi) of around 0.68 being obtained. Furthermore, it was found that increasing temperature from 25 ºC to 60 ºC enhances the reactivity significantly. The general kinetics data of EOR on Bi-decorated and bare THH Pd NCs have also been obtained, from the activation energy calculated based on Arrhenius plots, and compared. At the optimum Bi coverage, an enhancement in the activity of almost 3 times was achieved, and the corresponding activation energy was found to be reduced significantly.

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Fully Homomorphic Encryption (FHE) is a recently developed cryptographic technique which allows computations on encrypted data. There are many interesting applications for this encryption method, especially within cloud computing. However, the computational complexity is such that it is not yet practical for real-time applications. This work proposes optimised hardware architectures of the encryption step of an integer-based FHE scheme with the aim of improving its practicality. A low-area design and a high-speed parallel design are proposed and implemented on a Xilinx Virtex-7 FPGA, targeting the available DSP slices, which offer high-speed multiplication and accumulation. Both use the Comba multiplication scheduling method to manage the large multiplications required with uneven sized multiplicands and to minimise the number of read and write operations to RAM. Results show that speed up factors of 3.6 and 10.4 can be achieved for the encryption step with medium-sized security parameters for the low-area and parallel designs respectively, compared to the benchmark software implementation on an Intel Core2 Duo E8400 platform running at 3 GHz.

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Large integer multiplication is a major performance bottleneck in fully homomorphic encryption (FHE) schemes over the integers. In this paper two optimised multiplier architectures for large integer multiplication are proposed. The first of these is a low-latency hardware architecture of an integer-FFT multiplier. Secondly, the use of low Hamming weight (LHW) parameters is applied to create a novel hardware architecture for large integer multiplication in integer-based FHE schemes. The proposed architectures are implemented, verified and compared on the Xilinx Virtex-7 FPGA platform. Finally, the proposed implementations are employed to evaluate the large multiplication in the encryption step of FHE over the integers. The analysis shows a speed improvement factor of up to 26.2 for the low-latency design compared to the corresponding original integer-based FHE software implementation. When the proposed LHW architecture is combined with the low-latency integer-FFT accelerator to evaluate a single FHE encryption operation, the performance results show that a speed improvement by a factor of approximately 130 is possible.

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