Evaluating the quality of learning in Computer Supported Co-operative Learning

Can learning quality be maintained in the face of increasing class size by the use of Computer Supported Co-operative Learning (CSCL) technologies? In particular, can Computer-Mediated Communication promote critical thinking in addition to surface information transfer? We compared face-to-face seminars with asynchronous computer conferencing in the same Information Management class. From Garrison's theory of critical thinking and Henri's critical reasoning skills, we developed two ways of evaluating critical thinking: a student questionnaire and a content analysis technique. We found evidence for critical thinking in both situations, with some subtle differences in learning style. This paper provides an overview of this work.

An experiment in group learning technology: evaluating critical thinking in face-to-face and computer-supported seminars

Can learning quality be maintained in the face of increasing class size by the use of Computer Supported Co-operative Learning (CSCL) technologies? In particular, can Computer-Mediated Communication promote critical thinking in addition to surface information transfer? We compared face-to-face seminars with asynchronous computer conferencing in the same Information Management class. From Garrison's theory of critical thinking and Henri's critical reasoning skills, we developed two ways of evaluating critical thinking: a student questionnaire and a content analysis technique. We found evidence for critical thinking in both situations, with some subtle differences in learning style. This paper provides an overview of this work.

A content analysis method to measure critical thinking in face-to-face and computer supported group learning

This paper gives a detailed account of the content analysis method developed at Queen's University Belfast to measure critical thinking during group learning, as used in our controlled comparisons between learning in face-to-face and computer conference seminars. From Garrison's 5 stages of critical thinking, and Henri's cognitive skills needed in CMC, we have developed two research instruments: a student questionnaire and this content analysis method. The content analysis relies on identifying, within transcripts, examples of indicators of obviously critical and obviously uncritical thinking, from which several critical thinking ratios can be calculated.

Efficient FPGA Hardware Development: A Multi-Language Approach

This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high-level hardware design and efficient hardware implementation. The central idea of this framework is the integration of different hardware languages in a way that harnesses the best features of each language. This is illustrated in this paper by the integration of two hardware languages in the form of HIDE: a structured hardware language which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog, and Handel-C: an ANSI C-like hardware language which allows software and hardware engineers alike to target FPGAs from high-level algorithmic descriptions. On the one hand, HIDE has proven to be very successful in the description and generation of highly optimised parameterisable FPGA circuits from geometric descriptions. On the other hand, Handel-C has also proven to be very successful in the rapid design and prototyping of FPGA circuits from algorithmic application descriptions. The proposed integrated framework hence harnesses HIDE for the generation of highly optimised circuits for regular parts of algorithms, while Handel-C is used as a top-level design language from which HIDE functionality is dynamically invoked. The overall message of this paper posits that there need not be an exclusive choice between different hardware design flows. Rather, an integrated framework where different design flows can seamlessly interoperate should be adopted. Although the idea might seem simple prima facie, it could have serious implications on the design of future generations of hardware languages.

BSP -Style Computation: A Semantic Investigation

A BSP (Bulk Synchronous Parallelism) computation is characterized by the generation of asynchronous messages in packages during independent execution of a number of processes and their subsequent delivery at synchronization points. Bundling messages together represents a significant departure from the traditional ‘one communication at a time’ approach. In this paper the semantic consequences of communication packaging are explored. In particular, the BSP communication structure is identified with a general form of substitution—predicate substitution. Predicate substitution provides a means of reasoning about the synchronized delivery of asynchronous communications when the immediate programming context does not explicitly refer to the variables that are to be updated (unlike traditional operations, such as the assignment $x := e$, where the names of the updated variables can be extracted from the context). Proofs of implementations of Newton's root finding method and prefix sum are used to illustrate the practical application of the proposed approach.

Application-Specific Instruction Set Processor for SoC implementation of Modern Signal Processing Algorithms

A novel application-specific instruction set processor (ASIP) for use in the construction of modern signal processing systems is presented. This is a flexible device that can be used in the construction of array processor systems for the real-time implementation of functions such as singular-value decomposition (SVD) and QR decomposition (QRD), as well as other important matrix computations. It uses a coordinate rotation digital computer (CORDIC) module to perform arithmetic operations and several approaches are adopted to achieve high performance including pipelining of the micro-rotations, the use of parallel instructions and a dual-bus architecture. In addition, a novel method for scale factor correction is presented which only needs to be applied once at the end of the computation. This also reduces computation time and enhances performance. Methods are described which allow this processor to be used in reduced dimension (i.e., folded) array processor structures that allow tradeoffs between hardware and performance. The net result is a flexible matrix computational processing element (PE) whose functionality can be changed under program control for use in a wider range of scenarios than previous work. Details are presented of the results of a design study, which considers the application of this decomposition PE architecture in a combined SVD/QRD system and demonstrates that a combination of high performance and efficient silicon implementation are achievable. © 2005 IEEE.

Rapid Implementation and Optimisation of DSP Systems on FPGA-Centric Hetrogeneous Platforms

This paper, chosen as a best paper from the 2005 SAMOS Workshop on Computer Systems: describes the for the first time the major Abhainn project for automated system level design of embedded signal processing systems. In particular, this describes four key novelties: novel algorithm modelling techniques for DSP systems, automated implementation realisation, algorithm transformation for system optimisation and automated inter-processor communication. This is applied to two complex systems: a radar and sonar system. In both cases technology which allows non-experts to automatically create low-overhead, high performance embedded signal processing systems is exhibited.