Design optimisation of ring elements for broadband reflectarray antennas

Plane wave scattering from a flat surface consisting of two periodic arrays of ring elements printed on a grounded dielectric sheet is investigated. It is shown that the reflection phase variation as a function of ring diameter is controlled by the difference in the centre resonant frequency of the two arrays. Simulated and measured results at X-band demonstrate that this parameter can be used to reduce the gradient and improve the linearity of the reflection phase versus ring size slope. These are necessary conditions for the re-radiating elements to maximise the bandwidth of a microstrip reflectarray antenna. The scattering properties of a conventional dual resonant multilayer structure and an array of concentric rings printed on a metal backed dielectric substrate are compared and the trade-off in performance is discussed.

Rapid Implementation and Optimisation of DSP Systems on FPGA-Centric Hetrogeneous Platforms

This paper, chosen as a best paper from the 2005 SAMOS Workshop on Computer Systems: describes the for the first time the major Abhainn project for automated system level design of embedded signal processing systems. In particular, this describes four key novelties: novel algorithm modelling techniques for DSP systems, automated implementation realisation, algorithm transformation for system optimisation and automated inter-processor communication. This is applied to two complex systems: a radar and sonar system. In both cases technology which allows non-experts to automatically create low-overhead, high performance embedded signal processing systems is exhibited.

Optimisation of source/drain extension region profile for suppression of short channel effects in sub-50 nm DG SOI MOSFETs with high- k gate dielectrics

Novel technology dependent scaling parameters i.e. spacer to gradient ratio and effective channel length (Leff) are proposed for source/drain engineered DG MOSFET, and their significance in minimizing short channel effects (SCES) in high-k gate dielectrics is discussed in detail. Results show that a high-k dielectric should be associated with a higher spacer to gradient ratio to minimise SCEs The analytical model agrees with simulated data over the entire range of spacer widths, doping gradients, high-k gate dielectrics and effective channel lengths.