The last meal of the Late Ordovician mollusc ‘Helminthochiton’ thraivensis Reed, 1911, from the Lady Burn Starfish Beds, southwest Scotland.

An exceptional specimen of the Late Ordovician mollusc ‘Helminthochiton’ thraivensis Reed, from the Katian of the Lady Burn Starfish Beds, southwest Scotland, preserves gut contents that include nine pelmatozoan ossicles. These are interpreted as including two nodal and five intermodal columnals, and two radice ossicles from the attachment structure. The stem was cyclocyclic and heteromorphic, possibly N212. Radice ossicles were wider than the height of nodals, so radice scars must have encroached onto the latera of adjacent pluricolumnals. These features were compared with the 26 known pelmatozoan taxa from the Lady Burn Starfish Beds. Paracrinoids (one species) and glyptocystitid rhombiferans (six species) were discounted as prey because of their cemented attachment, and incorrect columnal morphology and lack of attachment, respectively. Of 19 species of crinoids, eight are discounted in which the column is pentagonal, tetragonal or unknown. Of the remaining eleven species, only the monobathrid camerate Macrostylocrinus cirrifer Ramsbottom satisfies all criteria for identification of the prey, including heteromorphy and radice scars encroaching adjacent internodals.

FPGA montgomery modular multiplication architectures suitable for ECCs over GF(p)

New FPGA architectures for the ordinary Montgomery multiplication algorithm and the FIOS modular multiplication algorithm are presented. The embedded 18×18-bit multipliers and fast carry look-ahead logic located on the Xilinx Virtex2 Pro family of FPGAs are used to perform the ordinary multiplications and additions/subtractions required by these two algorithms. The architectures are developed for use in Elliptic Curve Cryptosystems over GF(p), which require modular field multiplication to perform elliptic curve point addition and doubling. Field sizes of 128-bits and 256-bits are chosen but other field sizes can easily be accommodated, by rapidly reprogramming the FPGA. Overall, the larger the word size of the multiplier, the more efficiently it performs in terms of area/time product. Also, the FIOS algorithm is flexible in that one can tailor the multiplier architecture is to be area efficient, time efficient or a mixture of both by choosing a particular word size. It is estimated that the computation of a 256-bit scalar point multiplication over GF(p) would take about 4.8 ms.

Parish farms and the poor law: a response to unemployment in rural southern England, c.1815-1835

Finding a ‘solution’ for the seemingly intractable problem of unemployment in post-Napoleonic rural England was the Holy Grail for many vestries. Yet, whilst we know much about the depth and consequences of unemployment, parish-driven schemes to set the poor to work have been subjected to remarkably little in the way of systematic study. This paper focuses on one such policy that remains entirely obscure: parish farms, the hiring of pre-existing farms or fields by the parish on which to employ those out of work. Bearing a ‘family resemblance’ to allotments and other land-based attempts to alleviate poverty, parish farms were unique in that they were managed in all regards by the parish and were an employment strategy as opposed to a scheme to supplement the incomes of the poor. Whilst the archive of parish farms is often frustratingly opaque, it is shown that before they were effectively outlawed by the passing of the New Poor Law, many southern parishes, especially in the Weald of Kent and Sussex, adopted the scheme, occasionally with great success.

Improved Montgomery modular inverse algorithm

A new, single and unified Montgomery modular inverse algorithm, which performs both classical and Montgomery modular inversion, is proposed. This reduces the number of Montgomery multiplication operations required by 33% when compared with previous algorithms reported in the literature. The use of this in practice has been investigated by implementation of the improved unified algorithm and the previous algorithms on FPGA devices. The unified algorithm implementation shows a significant speed-up and a reduction in silicon area usage.