76 resultados para Modular simulators


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New FPGA architectures for the ordinary Montgomery multiplication algorithm and the FIOS modular multiplication algorithm are presented. The embedded 18×18-bit multipliers and fast carry look-ahead logic located on the Xilinx Virtex2 Pro family of FPGAs are used to perform the ordinary multiplications and additions/subtractions required by these two algorithms. The architectures are developed for use in Elliptic Curve Cryptosystems over GF(p), which require modular field multiplication to perform elliptic curve point addition and doubling. Field sizes of 128-bits and 256-bits are chosen but other field sizes can easily be accommodated, by rapidly reprogramming the FPGA. Overall, the larger the word size of the multiplier, the more efficiently it performs in terms of area/time product. Also, the FIOS algorithm is flexible in that one can tailor the multiplier architecture is to be area efficient, time efficient or a mixture of both by choosing a particular word size. It is estimated that the computation of a 256-bit scalar point multiplication over GF(p) would take about 4.8 ms.

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To develop real-time simulations of wind instruments, digital waveguides filters can be used as an efficient representation of the air column. Many aerophones are shaped as horns which can be approximated using conical sections. Therefore the derivation of conical waveguide filters is of special interest. When these filters are used in combination with a generalized reed excitation, several classes of wind instruments can be simulated. In this paper we present the methods for transforming a continuous description of conical tube segments to a discrete filter representation. The coupling of the reed model with the conical waveguide and a simplified model of the termination at the open end are described in the same way. It turns out that the complete lossless conical waveguide requires only one type of filter.Furthermore, we developed a digital reed excitation model, which is purely based on numerical integration methods, i.e., without the use of a look-up table.

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A new, single and unified Montgomery modular inverse algorithm, which performs both classical and Montgomery modular inversion, is proposed. This reduces the number of Montgomery multiplication operations required by 33% when compared with previous algorithms reported in the literature. The use of this in practice has been investigated by implementation of the improved unified algorithm and the previous algorithms on FPGA devices. The unified algorithm implementation shows a significant speed-up and a reduction in silicon area usage.

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Gas-liquid processing in microreactors remains mostly restricted to the laboratory scale due to the complexity and expenditure needed for an adequate numbering-up with a uniform flow distribution. Here, the numbering-up is presented for multi-phase (gas-liquid) flow in microreactor suitable for a production capacity of kg/h. Based on the barrier channels concept, the barrier-based micro/milli reactor (BMMR) is designed and fabricated to deliver flow non-uniformity of less than 10%. The BMMR consists of eight parallel channels all operated in the Taylor flow regime and with a liquid flow rate up to 150. mL/min. The quality of the flow distribution is reported by studying two aspects. The first aspect is the influence of different viscosities, surface tensions and flow rates. The second aspect is the influence of modularity by testing three different reaction channels type: (1) square channels fabricated in a stainless steel plate, (2) square channels fabricated in a glass plate, and (3) circular channels (capillaries) made of stainless steel. Additionally, the BMMR is compared to that of a single channel regard the slug and bubble lengths and bubble generation frequency. The results pave the ground for bringing multi-phase flow in microreactor one step closer for large scale production via numbering-up. © 2012 Elsevier B.V.

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This paper is concerned with assessing the building’s the energy efficiency and qualities of a modular design for the education industry, in order assess the long economic benefits. The research includes a life-cycle energy and cost analysis of the school building design, predicting the impact on the operational cost of the building as a result of the addition of photovoltaic panels. The paper also includes a comparative study between the ECO Modular Solutions building, and a current standard prefabricated school building, quantifying the savings in CO2 emissions and savings in cost.

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This paper describes the result of a project to develop climate adaptation design strategies funded by the UK’s Technology Strategy Board. The aim of the project was to look at the threats and opportunities presented by industrialized and house-building techniques in the light of predicted future increases in flooding and overheating due to anthropogenic climate change. The paper shows that the thermal performance of houses built to the current UK Building Regulations is not adequate to cope with changing weather patterns, and in light of this, develops a detailed design for a new house: one that is industrially produced and climatically resilient, but affordable. This detailed concept IDEAhaus of a modular house is not only flood-proof to a water depth of 750 mm, but also is designed to utilize passive cooling, which dramatically reduces the amount of overheating, both now and in the future.

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Large loads result in expensive foundations which are a substantial proportion of the capital cost of flap-type Wave Energy Converters (WECs). Devices such as Oyster 800, currently deployed at the European Marine Energy Centre (EMEC), comprise a single flap for the full width of the machine. Splitting a flap-type device into smaller vertical flap modules, to make a ‘modular-flap’, might reduce the total foundation loads, whilst still providing acceptable performance in terms of energy conversion.
This paper investigates the foundation loads of an undamped modular-flap device, comparing them to those for a rigid flap of an equivalent width. Physical modelling in a wave tank is used, with loads recorded using a six degree of freedom (DoF) load cell. Both fatigue and extreme loading analysis was conducted. The rotations of the flaps were also recorded, using a motion-tracking system.

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Electrolytic capacitors are extensively used in power converters but they are bulky, unreliable, and have short lifetimes. This paper proposes a new capacitor-free high step-up dc-dc converter design for renewable energy applications such as photovoltaics (PVs) and fuel cells. The primary side of the converter includes three interleaved inductors, three main switches, and an active clamp circuit. As a result, the input current ripple is greatly reduced, eliminating the necessity for an input capacitor. In addition, zero voltage switching (ZVS) is achieved during switching transitions for all active switches, so that switching losses can be greatly reduced. Furthermore, a three-phase modular structure and six pulse rectifiers are employed to reduce the output voltage ripple. Since magnetic energy stored in the leakage inductance is recovered, the reverse-recovery issue of the diodes is effectively solved. The proposed converter is justified by simulation and experimental tests on a 1-kW prototype.

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The overall aim of the work presented in this paper has been to develop Montgomery modular multiplication architectures suitable for implementation on modern reconfigurable hardware. Accordingly, novel high-radix systolic array Montgomery multiplier designs are presented, as we believe that the inherent regular structure and absence of global interconnect associated with these, make them well-suited for implementation on modern FPGAs. Unlike previous approaches, each processing element (PE) comprises both an adder and a multiplier. The inclusion of a multiplier in the PE means that the need to pre-compute or store any multiples of the operands is avoided. This also allows very high-radix implementations to be realised, further reducing the amount of clock cycles per modular multiplication, while still maintaining a competitive critical delay. For demonstrative purposes, 512-bit and 1024-bit FPGA implementations using radices of 2(8) and 2(16) are presented. The subsequent throughput rates are the fastest reported to date.