Scaling up strategies of the chronic respiratory disease programme of the European Innovation Partnership on Active and Healthy Ageing (Action Plan B3: Area 5)

Action Plan B3 of the European Innovation Partnership on Active and Healthy Ageing (EIP on AHA) focuses on the integrated care of chronic diseases. Area 5 (Care Pathways) was initiated using chronic respiratory diseases as a model. The chronic respiratory disease action plan includes (1) AIRWAYS integrated care pathways (ICPs), (2) the joint initiative between the Reference site MACVIA-LR (Contre les MAladies Chroniques pour un VIeillissement Actif) and ARIA (Allergic Rhinitis and its Impact on Asthma), (3) Commitments for Action to the European Innovation Partnership on Active and Healthy Ageing and the AIRWAYS ICPs network. It is deployed in collaboration with the World Health Organization Global Alliance against Chronic Respiratory Diseases (GARD). The European Innovation Partnership on Active and Healthy Ageing has proposed a 5-step framework for developing an individual scaling up strategy: (1) what to scale up: (1-a) databases of good practices, (1-b) assessment of viability of the scaling up of good practices, (1-c) classification of good practices for local replication and (2) how to scale up: (2-a) facilitating partnerships for scaling up, (2-b) implementation of key success factors and lessons learnt, including emerging technologies for individualised and predictive medicine. This strategy has already been applied to the chronic respiratory disease action plan of the European Innovation Partnership on Active and Healthy Ageing.

5-Fluorouracil: mechanisms of action and clinical strategies

5-fluorouracil (5-FU) is widely used in the treatment of cancer. Over the past 20 years, increased understanding of the mechanism of action of 5-FU has led to the development of strategies that increase its anticancer activity. Despite these advances, drug resistance remains a significant limitation to the clinical use of 5-FU. Emerging technologies, such as DNA microarray profiling, have the potential to identify novel genes that are involved in mediating resistance to 5-FU. Such target genes might prove to be therapeutically valuable as new targets for chemotherapy, or as predictive biomarkers of response to 5-FU-based chemotherapy.

Multidimensional DSP Core Synthesis for FPGA

This paper, chosen as a best paper from the 2004 SAMOS Workshop on Computer Systems: describes a novel, efficient methodology for automatically creating embedded DSP computer systems. The novelty arises since now embedded electronic signal processing systems, such as radar or sonar, can be designed by anyone from the algorithm level, i.e. no low level system design experience is required, whilst still achieving low controllable implementation overheads and high real time performance. In the chosen design example, a bank of Normalised Lattice Filter (NLF) components is created which a four-fold reduction in the required processing resource with no performance decrease.

Packet classification by multi-level cutting of the classification space: An algorithmic-architectural solution for IP packet classification in next generation networks

Traditionally, the Internet provides only a “best-effort” service, treating all packets going to the same destination equally. However, providing differentiated services for different users based on their quality requirements is increasingly becoming a demanding issue. For this, routers need to have the capability to distinguish and isolate traffic belonging to different flows. This ability to determine the flow each packet belongs to is called packet classification. Technology vendors are reluctant to support algorithmic solutions for classification due to their non-deterministic performance. Although CAMs are favoured by technology vendors due to their deterministic high lookup rates, they suffer from the problems of high power dissipation and high silicon cost. This paper provides a new algorithmic-architectural solution for packet classification that mixes CAMs with algorithms based on multi-level cutting the classification space into smaller spaces. The provided solution utilizes the geometrical distribution of rules in the classification space. It provides the deterministic performance of CAMs, support for dynamic updates, and added flexibility for system designers.

Packet classification by multi-level cutting of the classification space

Traditionally, the Internet provides only a “best-effort” service, treating all packets going to the same destination equally. However, providing differentiated services for different users based on their quality requirements is increasingly becoming a demanding issue. For this, routers need to have the capability to distinguish and isolate traffic belonging to different flows. This ability to determine the flow each packet belongs to is called packet classification. Technology vendors are reluctant to support algorithmic solutions for classification due to their nondeterministic performance. Although content addressable memories (CAMs) are favoured by technology vendors due to their deterministic high-lookup rates, they suffer from the problems of high-power consumption and high-silicon cost. This paper provides a new algorithmic-architectural solution for packet classification that mixes CAMs with algorithms based on multilevel cutting of the classification space into smaller spaces. The provided solution utilizes the geometrical distribution of rules in the classification space. It provides the deterministic performance of CAMs, support for dynamic updates, and added flexibility for system designers.

Memory-Centric Hardware Synthesis from Dataflow Models

Generation of hardware architectures directly from dataflow representations is increasingly being considered as research moves toward system level design methodologies. Creation of networks of IP cores to implement actor functionality is a common approach to the problem, but often the memory sub-systems produced using these techniques are inefficiently utilised. This paper explores some of the issues in terms of memory organisation and accesses when developing systems from these high level representations. Using a template matching design study, challenges such as modelling memory reuse and minimising buffer requirements are examined, yielding results with significantly less memory requirements and costly off-chip memory accesses.

Characterisation of protein stability in rod-insert vaginal rings

A major goal in vaccine development is elimination of the ‘cold chain’, the transport and storage system for maintenance and distribution of the vaccine product. This is particularly pertinent to liquid formulation of vaccines. We have previously described the rod-insert vaginal ring (RiR) device, comprising an elastomeric body into which are inserted lyophilised, rod-shaped, solid drug dosage forms, and having potential for sustained mucosal delivery of biomacromolecules, such as HIV envelope protein-based vaccine candidates. Given the solid, lyophilised nature of these insert dosage forms, we hypothesised that antigen stability may be significantly increased compared with more conventional solubilised vaginal gel format. In this study, we prepared and tested vaginal ring devices fitted with lyophilised rod inserts containing the model antigen bovine serum albumin (BSA). Both the RiRs and the gels that were freeze-dried to prepare the inserts were evaluated for BSA stability using PAGE, turbidimetry, microbial load, MALDI-TOF and qualitative precipitate solubility measurements. When stored at 4 oC, but not when stored at 40 oC / 75% RH, the RiR formulation offered protection against structural and conformational changes to BSA. The insert also retained matrix integrity and release characteristics. The results demonstrate that lypophilised gels can provide relative protection against degradation at lower temperatures compared to semi-solid gels. The major mechanism of degradation at 40 oC / 75% RH was shown to be protein aggregation. Finally, in a preliminary study, we found that addition of trehalose to the formulation significantly reduces the rate of BSA degradation as compared to the original formulation when stored at 40 oC /75% RH. Establishing the mechanism of degradation, and finding that degradation is decelerated in the presence of trehalose, will help inform further development of RiRs specifically and polymer based freeze-dried systems in general.

A Kernel Interleaved Scheduling Method for Streaming Applications on Soft-core Vector Processors

Massively parallel networks of highly efficient, high performance Single Instruction Multiple Data (SIMD) processors have been shown to enable FPGA-based implementation of real-time signal processing applications with performance and
cost comparable to dedicated hardware architectures. This is achieved by exploiting simple datapath units with deep processing pipelines. However, these architectures are highly susceptible to pipeline bubbles resulting from data and control hazards; the only way to mitigate against these is manual interleaving of
application tasks on each datapath, since no suitable automated interleaving approach exists. In this paper we describe a new automated integrated mapping/scheduling approach to map algorithm tasks to processors and a new low-complexity list scheduling technique to generate the interleaved schedules. When applied to a spatial Fixed-Complexity Sphere Decoding (FSD) detector
for next-generation Multiple-Input Multiple-Output (MIMO) systems, the resulting schedules achieve real-time performance for IEEE 802.11n systems on a network of 16-way SIMD processors on FPGA, enable better performance/complexity balance than current approaches and produce results comparable to handcrafted implementations.

Automatic FPGA Synthesis of Memory Intensive C-based Kernels

Realising high performance image and signal processing
applications on modern FPGA presents a challenging implementation problem due to the large data frames streaming through these systems. Specifically, to meet the high bandwidth and data storage demands of these applications, complex hierarchical memory architectures must be manually specified
at the Register Transfer Level (RTL). Automated approaches which convert high-level operation descriptions, for instance in the form of C programs, to an FPGA architecture, are unable to automatically realise such architectures. This paper
presents a solution to this problem. It presents a compiler to automatically derive such memory architectures from a C program. By transforming the input C program to a unique dataflow modelling dialect, known as Valved Dataflow (VDF), a mapping and synthesis approach developed for this dialect can
be exploited to automatically create high performance image and video processing architectures. Memory intensive C kernels for Motion Estimation (CIF Frames at 30 fps), Matrix Multiplication (128x128 @ 500 iter/sec) and Sobel Edge Detection (720p @ 30 fps), which are unrealisable by current state-of-the-art C-based synthesis tools, are automatically derived from a C description of the algorithm.