Progressive loss of ferroelectricity under bipolar pulsed fields and experimental determination of non-switchable polarization in Au/Ba0.5Sr0.5TiO3/SrRuO3 thin-film capacitors

175 nm-thick Ba0.5Sr0.5TiO3 (BST) thin film fabricated by pulsed laser deposition (PLD) technique is found to be a mixture of two distributions of material. We discuss whether these two components are nano-regions of paraelectric and ferroelectric phases, or a bimodal grain-size distribution, or an effect of oxygen vacancy gradient from the electrode interface. The fraction of switchable ferroelectric phase decreases under bipolar pulsed fields, but it recovers after removal of the external fields. The plot of capacitance in decreasing dc voltage (C(Vdown arrow) versus that in increasing dc 61 voltage C(Vup arrow) is a superposition of overlapping of two triangles, in contrast to one well-defined triangle for typical ferroelectric SrBi2Ta2O9 thin films.

Understanding thickness effects in thin film capacitors

Pulsed Laser Deposition (PLD) was used to make Au/(Ba0.5Sr0.5)TiO3/(La0.5Sr0.5) CoO3/MgO thin film capacitor structures. Functional properties were studied with changing BST thickness from similar to1265 nm to similar to63 nm. The dielectric constant was found to decrease, and migration of T-m (the temperature at which the dielectric constant is maximum) to lower temperatures occurred as thickness was reduced. Curie-Weiss plots of the as-obtained dielectric data, indicated that the Curie temperature was also systemmatically progressively depressed. Further, fitting to expressions previously used to describe diffuse phase transitions suggested increased diffuseness in transformation behaviour as film thickness decreased. This paper discusses the care needed in interpreting the observations given above. We make particular distinction between the apparent Curie-temperature derived from Curie-Weiss plots of as-measured data, and the inherent Curie temperature determined after correction for the interfacial capacitance. We demonstrate that while the apparent Curie temperature decreases as thickness decreases, the inherent Curie temperature is thickness independent. Thickness-invariant phase transition behaviour is confirmed from analysis of polarisation loops, and from examination of the temperature dependence of the loss-tangent. We particularly note that correction of data for interfacial capacitance does not alter the position of T-m. We must therefore conclude that the position of T-m is not related simply to phase transformation behaviour in BST thin films.

Idealised operation of zero-voltage-switching series-L/parallel-tuned Class-E power amplifier

An analysis of a modified series-L/parallel-tuned Class-E power amplifier is presented, which includes the effects that a shunt capacitance placed across the switching device will have on Class-E behaviour. In the original series L/parallel-tuned topology in which the output transistor capacitance is not inherently included in the circuit, zero-current switching (ZCS) and zero-current derivative switching (ZCDS) conditions should be applied to obtain optimum Class-E operation. On the other hand, when the output transistor capacitance is incorporated in the circuit, i.e. in the modified series-L/parallel-tuned topology, the ZCS and ZCDS would not give optimum operation and therefore zero-voltage-switching (ZVS) and zero-voltage-derivative switching (ZVDS) conditions should be applied instead. In the modified series-L/parallel-tuned Class-E configuration, the output-device inductance and the output-device output capacitance, both of which can significantly affect the amplifier's performance at microwave frequencies, furnish part, if not all, of the series inductance L and the shunt capacitance COUT, respectively. Further, when compared with the classic shunt-C/series-tuned topology, the proposed Class-E configuration offers some advantages in terms of 44% higher maximum operating frequency (fMAX) and 4% higher power-output capability (PMAX). As in the classic topology, the fMAX of the proposed amplifier circuit is reached when the output-device output capacitance furnishes all of the capacitance COUT, for a given combination of frequency, output power and DC supply voltage. It is also shown that numerical simulations agree well with theoretical predictions.

Exploring figures of merit associated with the suboptimum operation of class-E power amplifiers

Closed-form design equations for the operation of a class-E amplifier for zero switch voltage slope and arbitrary duty cycle are derived. This approach allows an additional degree of freedom in the design of class-E amplifiers which are normally designed for 50 duty ratio. The analysis developed permits the selection of non-unique solutions where amplifier efficiency is theoretically 100 but power output capability is less than that the 50 duty ratio case would permit. To facilitate comparison between 50 (optimal) and non-50 (suboptimal) duty ratio cases, each important amplifier parameter is normalised to its corresponding optimum operation value. It is shown that by choosing a non-50 suboptimal solution, the operating frequency of a class-E amplifier can be extended. In addition, it is shown that by operating the amplifier in the suboptimal regime, other amplifier parameters, for example, transistor output capacitance or peak switch voltage, can be included along with the standard specification criteria of output power, DC supply voltage and operating frequency as additional input design specifications. Suboptimum class-E operation may have potential advantages for monolithic microwave integrated circuit realisation as lower inductance values (lower series resistance, higher self-resonance frequency, less area) may be required when compared with the results obtained for optimal class-E amplifier synthesis. The theoretical analysis conducted here was verified by harmonic balance simulation, with excellent agreement between both methods. © The Institution of Engineering and Technology 2007.

Analog performance of double gate SOI transistors

Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.

Size Effects on Thin Film Ferroelectrics: Experiments on Isolated Single Crystal Sheets

Thin lamellae were cut from bulk single crystal BaTiO3 using a Focused Ion Beam Microscope. They were then removed and transferred onto single crystal MgO substrates, so that their functional properties could be measured independent of the original host bulk ferroelectric. The temperature dependence of the capacitance of these isolated single crystal films was found to be strongly bulk-like, demonstrating a sharp Curie anomaly, as well as Curie-Weiss behaviour. In addition, the sudden change in the remanent polarisation as a function of temperature at TC was characteristic of a first order phase change. The work represents a dramatic improvement on that previously published by M. M. Saad, P. Baxter, R. M. Bowman, J. M. Gregg, F. D. Morrison & J. F. Scott, J. Phys: Cond. Matt., 16 L451-L456 (2004), as critical shortcomings in the original specimen geometry, involving potential signal contributions from bulk BaTiO3, have now been obviated. That the functional properties of single crystal thin film lamellae are comparable to bulk, and not like those of conventionally deposited heteroegenous thin film systems, has therefore been confirmed.

Periodically loaded dipole array supporting left-handed propagation

Periodically loaded dipole arrays printed on grounded dielectric substrate are shown to exhibit left-handed propagation properties. In an equivalent transmission line representation, lefthandedness emerges due to the excess series capacitance and shunt inductance. Based on this concept, the authors study the distribution of the modal fields and the variation of series capacitance and shunt inductance as the dipoles are loaded with stubs. Full wave dispersion curves that show the gradual transition from a right-handed to a left-handed medium upon periodically loading the dipoles with stubs are presented. An equivalent circuit is derived that matches to a very good extent the full wave result. The cell dimensions are a small fraction of the wavelength (),15), so the structure can be considered as an equivalent homogeneous surface. The structure is simple, readily scalable to higher frequencies and compatible with low-cost fabrication techniques.

Efficient modeling of novel uniplanar left-handed metamaterials

This paper presents an efficient. modeling technique for the derivation of the dispersion characteristics of novel uniplanar metallodielectric periodic structures. The analysis is based on the method of moments and an interpolation scheme, which significantly accelerates the computations. Triangular basis functions are used that allow for modeling of arbitrary shaped metallic elements. Based on this method, novel uniplanar left-handed (LH) metamaterials are proposed. Variations of the split rectangular-loop element printed on grounded dielectric substrate are demonstrated to possess LH propagation properties. Full-wave dispersion curves are presented. Based on the dual transmission-line concept, we study the distribution of the modal fields And the variation of series capacitance and shunt inductance for all the proposed elements. A verification of the left-handedness is presented by means of full-wave simulation of finite uniplanar arrays using commercial software (HFSS). The cell dimensions are a small fraction of the wavelength (approximately lambda/24) so that the structures can he considered as a homogeneous effective medium. The structures are simple, readily scalable to higher frequencies, and compatible with low-cost fabrication techniques.

Series-L/parallel-tuned comparison with shunt-C/series-tuned class-E power amplifier

An analysis of the operation of a series-L/parallel-tuned class-E amplifier and its equivalence to the classic shunt-C/series-tuned class-E amplifier are presented. The first reported closed form design equations for the series-L/parallel-tuned topology operating under ideal switching conditions are given. Furthermore, a design procedure is introduced that allows the effect that nonzero switch resistance has on amplifier performance efficiency to be accounted for. The technique developed allows optimal circuit components to be found for a given device series resistance. For a relatively high value of switching device ON series resistance of 4O, drain efficiency of around 66% for the series-L/parallel-tuned topology, and 73% for the shunt-C/series-tuned topology appear to be the theoretical limits. At lower switching device series resistance levels, the efficiency performance of each type are similar, but the series-L/parallel-tuned topology offers some advantages in terms of its potential for MMIC realisation. Theoretical analysis is confirmed by numerical simulation for a 500mW (27dBm), 10% bandwidth, 5 V series-L/parallel-tuned, then, shunt-C/series-tuned class E power amplifier, operating at 2.5 GHz, and excellent agreement between theory and simulation results is achieved. The theoretical work presented in the paper should facilitate the design of high-efficiency switched amplifiers at frequencies commensurate with the needs of modern mobile wireless applications in the microwave frequency range, where intrinsically low-output-capacitance MMIC switching devices such as pHEMTs are to be used.

The Effect of Antinotches on Domain Wall Mobility in Single Crystal Ferroelectric Nanowires

Changes in domain wall mobility, caused by the presence of antinotches in single crystal BaTiO3 nanowires, have been investigated. While antinotches appeared to cause a slight broadening in the distribution of switching events, observed as a function of applied electric field (inferred from capacitance-voltage measurements), the effect was often subtle. Greater clarity of information was obtained from Rayleigh analysis of the capacitance variation with ac field amplitude. Here the magnitude of the domain wall mobility parameter (R) associated with irreversible wall movements was found to be reduced by the presence of antinotches - an effect which became more noticeable on heating toward the Curie temperature. The reduction in this domain wall mobility was contrasted with the noticeable enhancement found previously in ferroelectric wires with notches. Finite element modeling of the electric field, developed in the nanowires during switching, revealed regions of increased and decreased local field at the center of the notch and antinotch structures, respectively; the absolute magnitude of field enhancement in the notch centers was considerably greater than the field reduction in the center of the antinotches and this was commensurate with the manner in, and degree to, which domain wall mobility appeared to be affected. We therefore conclude that the main mechanism by which morphology alters the irreversible component of the domain wall mobility in ferroelectric wire structures is via the manner in which morphological variations alter the spatial distribution of the electric field.

Barrier height variations and interface properties of PtSi/Si structures

To study some of the interfacial properties of PtSi/Si diodes, Schottky structures were fabricated on (100) crystalline silicon substrates by conventional thermal evaporation of Pt on Si followed by annealing at different temperatures (from 400 degrees C to 700 degrees C) to form PtSi. The PtSi/n-Si diodes, all yielded Schottky barrier (SB) heights that are remarkably temperature dependent. The temperature range (20-290 K) over which the I-V characteristics were measured in the present study is broader with a much lower limit (20 K), than what is usually reported in literature. These variations in the barrier height are adequately interpreted by introducing spatial inhomogeneity into the barrier potential with a Gaussian distribution having a mean barrier of 0.76 eV and a standard deviation of 30 meV. Multi-frequency capacitance-voltage measurements suggest that the barrier is primarily controlled by the properties of the silicide-silicon interface. The forward C-V characteristics, in particular, show small peaks at low frequencies that can be ascribed to interface states rather than to a series resistance effect.

Phase synchronization from noisy univariate signals

We present methods for detecting phase synchronization of two unidirectionally coupled, self-sustained noisy oscillators from a signal of the driven oscillator alone. One method detects soft phase locking; another hard phase locking. Both are applied to the problem of detecting phase synchronization in von Karman vortex flow meters.

Data-driven optimal filtering for phase and frequency of noisy oscillations: Application to vortex flow metering

A method for measuring the phase of oscillations from noisy time series is proposed. To obtain the phase, the signal is filtered in such a way that the filter output has minimal relative variation in the amplitude over all filters with complex-valued impulse response. The argument of the filter output yields the phase. Implementation of the algorithm and interpretation of the result are discussed. We argue that the phase obtained by the proposed method has a low susceptibility to measurement noise and a low rate of artificial phase slips. The method is applied for the detection and classification of mode locking in vortex flow meters. A measure for the strength of mode locking is proposed.

Design of hydraulic structures considering different sheetpile configurations and flow through canal banks

This research investigated seepage under hydraulic structures considering flow through the banks of the canal. A computer model, utilizing the finite element method, was used. Different configurations of sheetpile driven under the floor of the structure were studied. Results showed that the transverse extension of sheetpile, driven at the middle of the floor, into the banks of the canal had very little effect on seepage losses, uplift force, and on the exit gradient at the downstream end of the floor. Likewise, confining the downstream floor with sheetpile from three sides was not found effective. When the downstream floor was confined with sheetpile from all sides, this has significantly reduced the exit gradient. Furthermore, all the different configurations of the sheetpile had insignificant effect on seepage losses. The most effective configuration of the sheetpile was the case when two rows of sheetpiles were driven at the middle and at the downstream end of the floor, with the latter sheetpile extended few meters into the banks of the canal. This case has significantly reduced the exit gradient and caused only slight increase in the uplift force when compared to other sheetpile configurations. The present study suggests that two-dimensional analysis of seepage problems underestimates the exit gradient and uplift force on hydraulic structures.

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano-circuit simulation. The FinFET used in this work is designed using careful engineering of source-drain extension, which simultaneously improves maximum frequency of oscillation f(max) because of lower gate to drain capacitance, and intrinsic gain A(V0) = g(m)/g(ds), due to lower output conductance g(ds). The framework for the ANN-based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I-d on drain-source V-ds and gate-source V-gs is derived by a simple two-layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low-noise amplifier. At low power (J(ds) similar to 10 mu A/mu m) improvement was observed in both third-order-intercept IIP3 (similar to 10 dBm) and intrinsic gain A(V0) (similar to 20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first-order to third-order derivative of I-d with respect to gate voltage and lower g(ds), in FinFET compared to bulk MOSFET. Copyright (C) 2009 John Wiley & Sons, Ltd.