Analysis and Synthesis of pHEMT Class-E Amplifiers with Shunt Inductor including ON-State Active-Device Resistance Effects

In this theoretical paper, the analysis of the effect that ON-state active-device resistance has on the performance of a Class-E tuned power amplifier using a shunt inductor topology is presented. The work is focused on the relatively unexplored area of design facilitation of Class-E tuned amplifiers where intrinsically low-output-capacitance monolithic microwave integrated circuit switching devices such as pseudomorphic high electron mobility transistors are used. In the paper, the switching voltage and current waveforms in the presence of ON-resistance are analyzed in order to provide insight into circuit properties such as RF output power, drain efficiency, and power-output capability. For a given amplifier specification, a design procedure is illustrated whereby it is possible to compute optimal circuit component values which account for prescribed switch resistance loss. Furthermore, insight into how ON-resistance affects transistor selection in terms of peak switch voltage and current requirements is described. Finally, a design example is given in order to validate the theoretical analysis against numerical simulation.

SiGe HBTs on Bonded SOI Incorporating Buried Silicide Layers

The performance of silicon bipolar transistors has been significantly improved by the use of ultra narrow base layers of SiGe. To further improve device performance by minimising parasitic resistance and capacitance the authors produced an unique silicon-on-insulator (SOI) substrate incorporating a buried tungsten disilicide layer. This structure forms the basis of a recent submission by Zarlink Semiconductors ( Silvaco, DeMontfort & Queen�s) to DTI for high voltage devices for automotive applications. The Queen�s part of the original EPSRC project was rated as tending to outstanding.

Plasma dynamics in an inductively coupled magnetic neutral loop discharge

Magnetic neutral loop discharges (NLDs) can be operated at significantly lower pressures than conventional radio-frequency (rf) inductively coupled plasmas (ICPs). These low pressure conditions are favourable for technological applications, in particular anisotropic etching. An ICP–NLD has been designed providing excellent diagnostics access for detailed investigations of fundamental mechanisms. Spatially resolved Langmuir probe measurements have been performed in the plasma production region (NL region) as well as in the remote application region downstream from the NL region. Depending on the NL gradient two different operation modes have been observed exhibiting different opportunities for control of plasma uniformity. The efficient operation at comparatively low pressures results in ionization degrees exceeding 1%. In this regime neutral dynamics has to be considered and can influence neutral gas and process uniformity. Neutral gas depletion through elevated gas temperatures and high ionization rates have been quantified. At pressures above 0.1 Pa, gas heating is the dominant depletion mechanism. At lower pressures neutral gas is predominantly depleted through high ionization rates and rapid transport of ions by ambipolar diffusion along the magnetic field lines. Non-uniform profiles of the ionization rate can, therefore, result in localized neutral gas depletion and non-uniform processing. We have also investigated the electron dynamics within the radio-frequency cycle using phase resolved optical emission spectroscopy and Thomson scattering. In these measurements electron drift phenomena along the NL torus have been identified.

Neutral gas depletion mechanisms in dense low-temperature argon plasmas

Neutral gas depletion mechanisms are investigated in a dense low-temperature argon plasma-an inductively coupled magnetic neutral loop (NL) discharge. Gas temperatures are deduced from the Doppler profile of the 772.38 nm line absorbed by argon metastable atoms. Electron density and temperature measurements reveal that at pressures below 0.1 Pa, relatively high degrees of ionization (exceeding 1%) result in electron pressures, p(e) = kT(e)n(e), exceeding the neutral gas pressure. In this regime, neutral dynamics has to be taken into account and depletion through comparatively high ionization rates becomes important. This additional depletion mechanism can be spatially separated due to non-uniform electron temperature and density profiles (non-uniform ionization rate), while the gas temperature is rather uniform within the discharge region. Spatial profiles of the depletion of metastable argon atoms in the NL region are observed by laser induced fluorescence spectroscopy. In this region, the depletion of ground state argon atoms is expected to be even more pronounced since in the investigated high electron density regime the ratio of metastable and ground state argon atom densities is governed by the electron temperature, which peaks in the NL region. This neutral gas depletion is attributed to a high ionization rate in the NL zone and fast ion loss through ambipolar diffusion along the magnetic field lines. This is totally different from what is observed at pressures above 10 Pa where the degree of ionization is relatively low (

Even order harmonic Series-L/Parallel-Tuned Class-E frequency multiplier

In this brief, we propose a new Class-E frequency multiplier based on the recently introduced Series-L/Parallel-Tuned Class-E amplifier. The proposed circuit produces even-order output harmonics. Unlike previously reported solutions the proposed circuit can operate under 50% duty ratio which minimizes the conduction losses. The circuit also offers the possibility for increased maximum operating frequency, reduced peak switch voltage, higher load resistance and inherent bond wire absorption; all potentially useful in monolithic microwave integrated circuit implementations. In addition, the circuit topology suggested large transistors with high output capacitances can be deployed. Theoretical design equations are given and the predictions made using these are shown to agree with harmonic balance circuit simulation results.

Germanium on Sapphire By Wafer Bonding

This paper describes the creation of a germanium on sapphire platform, via wafer bonding technology, for system-on-a-chip applications. Similar thermal coefficients of expansion between germanium (5.8 x 10-6 K-1) and sapphire (5 x 10-6 K-1) make the bonding of germanium to sapphire a reality. Germanium directly bonded to sapphire results in microvoid generation during post bond annealing. Inclusion of an interface layer such as silicon dioxide layer by plasma enhanced chemical vapour deposition, prior to bonding, results in a microvoid free bond interface after annealing. Grinding and polishing of the subsequent germanium layer has been achieved leaving a thick germanium on sapphire (GeOS) substrate. Submicron GeOS layers have also been achieved with hydrogen/helium co-implantation and layer transfer. Circular geometry transistors exhibiting a field effect mobility of 890 cm2/V s have been fabricated onto the thick germanium on sapphire layer.

Germanium on sapphire

This paper explores the potential of germanium on sapphire (GeOS) wafers as a universal substrate for System on a Chip (SOC), mm wave integrated circuits (MMICs) and optical imagers. Ge has a lattice constant close to that of GaAs enabling epitaxial growth. Ge, GaAs and sapphire have relatively close temperature coefficients of expansion (TCE), enabling them to be combined without stress problems. Sapphire is transparent over the range 0.17 to 5.5 µm and has a very low loss tangent (a) for frequencies up to 72 GHz. Ge bonding to sapphire substrates has been investigated with regard to micro-voids and electrical quality of the Ge back interface. The advantages of a sapphire substrate for integrated inductors, coplanar waveguides and crosstalk suppression are also highlighted. MOS transistors have been fabricated on GeOS substrates, produced by the Smart-cut process, to illustrate the compatibility of the substrate with device processing. © 2008 World Scientific Publishing Company.

Ultra-lightweight true random number generators

A series of ultra-lightweight digital true random number generators (TRNGs) are presented. These TRNGs are based on the observation that, when a circuit switches from a metastable state to a bi-stable state, the resulting state may be random. Four such circuits with low hardware cost are presented: one uses an XOR gate; one uses a lookup table; one uses a multiplexer and an inverter; and one uses four transistors. The three TRNGs based on the first three circuits are implemented on a field programmable gate array and successfully pass the DIEHARD RNG tests and the National Institute of Standard and Technology (NIST) RNG tests. To the best of the authors' knowledge, the proposed TRNG designs are the most lightweight among existing TRNGs.

Fabrication and characterisation of high resistivity SOI substrates for monolithic high energy physics detectors

Silicon on Insulator (SOI) substrates offer a promising platform for monolithic high energy physics detectors with integrated read-out electronics and pixel diodes. This paper describes the fabrication and characterisation of specially-configured SOI substrates using improved bonded wafer ion split and grind/polish technologies. The crucial interface between the high resistivity handle silicon and the SOI buried oxide has been characterised using both pixel diodes and circular geometry MOS transistors. Pixel diode breakdown voltages were typically greater than 100V and average leakage current densities at 70 V were only 55 nA/ sq cm. MOS transistors subjected to 24 GeV proton irradiation showed an increased SOI buried oxide trapped charge of only 3.45x1011cn-2 for a dose of 2.7Mrad

64-point Fourier transform chip for digital television applications

A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.

A 64-point fourier transform chip for video motion compensation using phase correlation

Details of a new low power fast Fourier transform (FFT) processor for use in digital television applications are presented. This has been fabricated using a 0.6-µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8 × 8 mm and dissipates 1 W. The chip design is based on a novel VLSI architecture which has been derived from a first principles factorization of the discrete Fourier transform (DFT) matrix and tailored to a direct silicon implementation.

Rapid design of a single chip adaptive beamformer

This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 GigaFlops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realize the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilization of a library of parameterizable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.

Error analysis of FFT architectures for digital video applications

This paper describes how worst-case error analysis can be applied to solve some of the practical issues in the development and implementation of a low power, high performance radix-4 FFT chip for digital video applications. The chip has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W, leading to a cost-effective silicon solution for high quality video processing applications. The analysis focuses on the effect that different radix-4 architectural configurations and finite wordlengths has on the FFT output dynamic range. These issues are addressed using both mathematical error models and through extensive simulation.

New FFT architecture and chip design for motion compensation based on phase correlation

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.

Magnetic instability in a dilute circular rarefaction wave

The growth of magnetic fields in the density gradient of a rarefaction wave has been observed in simulations and in laboratory experiments. The thermal anisotropy of the electrons, which gives rise to the magnetic instability, is maintained by the ambipolar electric field. This simple mechanism could be important for the magnetic field amplification in astrophysical jets or in the interstellar medium ahead of supernova remnant shocks. The acceleration of protons and the generation of a magnetic field by the rarefaction wave, which is fed by an expanding circular plasma cloud, is examined here in form of a 2D particle-in-cell simulation. The core of the plasma cloud is modeled by immobile charges, and the mobile protons form a small ring close to the cloud's surface. The number density of mobile protons is thus less than that of the electrons. The protons of the rarefaction wave are accelerated to 1/10 of the electron thermal speed, and the acceleration results in a thermal anisotropy of the electron distribution in the entire plasma cloud. The instability in the rarefaction wave is outrun by a TM wave, which grows in the dense core distribution, and its magnetic field expands into the rarefaction wave. This expansion drives a secondary TE wave. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4769128]