From PASS 1 to YES to AND logic: building parallel processing into molecular logic gates by sequential addition of receptors

The synthesis and photophysical characterization of a novel molecular logic gate 4, operating in water, is demonstrated based on the competition between. fluorescence and photoinduced electron transfer (PET). It is constructed according to a 'fluorophore-spacer-receptor(1)-spacer-receptor(2)' format where anthracene is the. fluorophore, receptor(1) is a tertiary amine and receptor(2) is a phenyliminodiacetate ligand. Using only protons and zinc cations as the chemical inputs and. fluorescence as the output, 4 is demonstrated to be both a two-input AND and INH logic gate. When 4 is examined in context to the YES logic gates 1 and 2, and the two-input AND logic gate 3 and three-input AND logic gate 5, each with one or more of the following receptors including a tertiary amine, phenyliminodiacetate or benzo-15-crown-5 ether, logic gate 4 is the missing link in the homologous series. Collectively, the molecular logic gates 1-5 corroborate the PET 'fluorophore-spacer-receptor' model using chemical inputs and a light-signal output and provide insight into controlling the. fluorescence quantum yield of future PET-based molecular logic gates.

Application-Specific Instruction Set Processor for SoC implementation of Modern Signal Processing Algorithms

A novel application-specific instruction set processor (ASIP) for use in the construction of modern signal processing systems is presented. This is a flexible device that can be used in the construction of array processor systems for the real-time implementation of functions such as singular-value decomposition (SVD) and QR decomposition (QRD), as well as other important matrix computations. It uses a coordinate rotation digital computer (CORDIC) module to perform arithmetic operations and several approaches are adopted to achieve high performance including pipelining of the micro-rotations, the use of parallel instructions and a dual-bus architecture. In addition, a novel method for scale factor correction is presented which only needs to be applied once at the end of the computation. This also reduces computation time and enhances performance. Methods are described which allow this processor to be used in reduced dimension (i.e., folded) array processor structures that allow tradeoffs between hardware and performance. The net result is a flexible matrix computational processing element (PE) whose functionality can be changed under program control for use in a wider range of scenarios than previous work. Details are presented of the results of a design study, which considers the application of this decomposition PE architecture in a combined SVD/QRD system and demonstrates that a combination of high performance and efficient silicon implementation are achievable. © 2005 IEEE.

Co-design of Distributed Systems Using Skeleton and Autonomic Management Abstractions

We discuss how common problems arising with multi/many core distributed architectures can he effectively handled through co-design of parallel/distributed programming abstractions and of autonomic management of non-functional concerns. In particular, we demonstrate how restricted patterns (or skeletons) may be efficiently managed by rule-based autonomic managers. We discuss the basic principles underlying pattern+manager co-design, current implementations inspired by this approach and some result achieved with proof-or-concept, prototype.

Management in distributed systems: A semi-formal approach

The reverse engineering of a skeleton based programming environment and redesign to distribute management activities of the system and thereby remove a potential single point of failure is considered. The Ore notation is used to facilitate abstraction of the design and analysis of its properties. It is argued that Ore is particularly suited to this role as this type of management is essentially an orchestration activity. The Ore specification of the original version of the system is modified via a series of semi-formally justified derivation steps to obtain a specification of the decentralized management version which is then used as a basis for its implementation. Analysis of the two specifications allows qualitative prediction of the expected performance of the derived version with respect to the original, and this prediction is borne out in practice.

Rapid Implementation and Optimisation of DSP Systems on FPGA-Centric Hetrogeneous Platforms

This paper, chosen as a best paper from the 2005 SAMOS Workshop on Computer Systems: describes the for the first time the major Abhainn project for automated system level design of embedded signal processing systems. In particular, this describes four key novelties: novel algorithm modelling techniques for DSP systems, automated implementation realisation, algorithm transformation for system optimisation and automated inter-processor communication. This is applied to two complex systems: a radar and sonar system. In both cases technology which allows non-experts to automatically create low-overhead, high performance embedded signal processing systems is exhibited.