Differential susceptibility of mitochondrial complex II to inhibition by oxaloacetate in brain and heart

Mitochondrial Complex II is a key mitochondrial enzyme connecting the tricarboxylic acid (TCA) cycle and the electron transport chain. Studies of complex II are clinically important since new roles for this enzyme have recently emerged in cell signalling, cancer biology, immune response and neurodegeneration. Oxaloacetate (OAA) is an intermediate of the TCA cycle and at the same time is an inhibitor of complex II with high affinity (Kd ~ 10− 8 M). Whether or not OAA inhibition of complex II is a physiologically relevant process is a significant, but still controversial topic. We found that complex II from mouse heart and brain tissue has similar affinity to OAA and that only a fraction of the enzyme in isolated mitochondrial membranes (30.2 ± 6.0% and 56.4 ± 5.6% in the heart and brain, respectively) is in the free, active form. Since OAA could bind to complex II during isolation, we established a novel approach to deplete OAA in the homogenates at the early stages of isolation. In heart, this treatment significantly increased the fraction of free enzyme, indicating that OAA binds to complex II during isolation. In brain the OAA-depleting system did not significantly change the amount of free enzyme, indicating that a large fraction of complex II is already in the OAA-bound inactive form. Furthermore, short-term ischemia resulted in a dramatic decline of OAA in tissues, but it did not change the amount of free complex II. Our data show that in brain OAA is an endogenous effector of complex II, potentially capable of modulating the activity of the enzyme.

Constructive Synthesis of Memory-Intensive Accelerators for FPGA From Nested Loop Kernels

Field-programmable gate arrays are ideal hosts to custom accelerators for signal, image, and data processing but de- mand manual register transfer level design if high performance and low cost are desired. High-level synthesis reduces this design burden but requires manual design of complex on-chip and off-chip memory architectures, a major limitation in applications such as video processing. This paper presents an approach to resolve this shortcoming. A constructive process is described that can derive such accelerators, including on- and off-chip memory storage from a C description such that a user-defined throughput constraint is met. By employing a novel statement-oriented approach, dataflow intermediate models are derived and used to support simple ap- proaches for on-/off-chip buffer partitioning, derivation of custom on-chip memory hierarchies and architecture transformation to ensure user-defined throughput constraints are met with minimum cost. When applied to accelerators for full search motion estima- tion, matrix multiplication, Sobel edge detection, and fast Fourier transform, it is shown how real-time performance up to an order of magnitude in advance of existing commercial HLS tools is enabled whilst including all requisite memory infrastructure. Further, op- timizations are presented that reduce the on-chip buffer capacity and physical resource cost by up to 96% and 75%, respectively, whilst maintaining real-time performance.