Amplitude-modulation characteristics of power-combining Class-E amplifier with finite choke

Power back-off performances of a new variant power-combining Class-E amplifier under different amplitude-modulation schemes such as continuous wave (CW), envelope elimination and restoration (EER), envelope tracking (ET) and outphasing are for the first time investigated in this study. Finite DC-feed inductances rather than massive RF chokes as used in the classic single-ended Class-E power amplifier (PA) resulted from the approximate yet effective frequency-domain circuit analysis provide the wherewithal to increase modulation bandwidth up to 80% higher than the classic single-ended Class-E PA. This increased modulation bandwidth is required for the linearity improvement in the EER/ET transmitters. The modified output load network of the power-combining Class-E amplifier adopting three-harmonic terminations technique relaxes the design specifications for the additional filtering block typically required at the output stage of the transmitter chain. Qualitative agreements between simulation and measurement results for all four schemes were achieved where the ET technique was proven superior to the other schemes. When the PA is used within the ET scheme, an increase of average drain efficiency of as high as 40% with respect to the CW excitation was obtained for a multi-carrier input signal with 12 dB peak-to-average power ratio. © 2011 The Institution of Engineering and Technology.

Enhanced efficiency of envelope-tracking based broadband inverse class-E power amplifier

In this paper, the envelope-tracking technique is exploited to boost average efficiency of the newly introduced broadband Inverse Class-E power amplifier. A 2.26 GHz - 20.5 dBm - 3 V power amplifier was designed, constructed, and measured. For a multi-carrier input signal with 10 dB peak-to-average ratio, the average PAE was increased from 5.7% to 54.5%. © 2008 IEEE.

Power back-off behaviour of high-efficiency power-combining Class-E amplifier

Power back-off performances of the modified power-combining Class-E amplifier under different amplitudemodulation schemes such as envelope elimination and restoration (EER) and envelope tracking (ET) are experimentally assessed in this paper. The modified output load network adopting three-harmonic terminations technique eliminates the need for additional lossy filtering section in the transmitter chain. Small dc-feed inductances rather than massive RF chokes as in the classic Class-E amplifier are used so as to increase the modulation bandwidth and therefore improve the linearity of the EER transmitter. High efficiency over a wide dynamic range using amplitude modulation through drain-voltage control (EER) was achieved and this agrees well with the Class-E theoretical prediction. When the PA was used within the ET scheme, an increase of average drain efficiency of as high as 40% with respect to the CW excitation was obtained for a multi-carrier input signal with 12dB peak-to-average power ratio. © 2011 Institut fur Mikrowellen.

Coordinated Design of Phase Measurement Unit and Power System Stabilisers in Large Scale Power System

This paper presents a case-study of a PMU application with PSS support in a real large scale Chinese power system to suppress inter-area oscillations. The paper uses PMU measured feedback signals from a PSS input signal for dynamic torque analysis (DTA). In the paper, a mathematical model of multi-machine power system is described, followed by formation of the residue and DTA indices. Simulations of the model are used with a large-scale power system model to demonstrate the role of PSS and the equivalence of DTA residue indices.

Properties of two interlinked Chi(2) interactions in noncollinear phase matching

We present a compact experimental realization of the interaction among five field modes in a chi((2)) nonlinear crystal. The classical evolution of the fields can be analytically described assuming that two of the fields play the role of nondepleted pumps. A peculiar behavior appears that has been experimentally verified. If one of the fields has a nonzero input amplitude, then the other two fields at the output are holographic replicas of the input signal. (C) 2004 Optical Society of America

Physical modelling of millimetre wave signal reflection from forward biased PIN diodes

This paper examines the DC power requirements of PIN diodes which, with suitable applied DC bias, have the potential to reflect or to permit transmission of millimetre wave energy through them by the process of inducing a semiconductor plasma layer in the i-region. The study is conducted using device level simulation of SOI and bulk PIN diodes and reflection modelling based on the Drude conduction model. We examined five diode lengths (60–140 µm) and seven diode thicknesses (4–100 µm). Simulation output for the diodes of varying thicknesses was subsequently used in reflection modelling to assess their performance for 100 GHz operation. It is shown that substantially high DC input power is required in order to induce near total reflection in SOI PIN diodes at 100 GHz. Thinner devices consume less DC power, but reflect less incident radiation for given input power. SOI diodes are shown to have improved carrier confinement compared with bulk diodes.

Iterative Receiver Design for MIMO Systems with Improper Signal Constellations

In this paper, we propose a novel iterative receiver
strategy for uncoded multiple-input, multiple-output (MIMO)
systems employing improper signal constellations. The proposed
scheme is shown to achieve superior performance and faster
convergence without the loss of spectrum efficiency compared
to the conventional iterative receivers. The superiority of this
novel approach over conventional solutions is verified by both
simulation and analytical results.

Application-Specific Instruction Set Processor for SoC implementation of Modern Signal Processing Algorithms

A novel application-specific instruction set processor (ASIP) for use in the construction of modern signal processing systems is presented. This is a flexible device that can be used in the construction of array processor systems for the real-time implementation of functions such as singular-value decomposition (SVD) and QR decomposition (QRD), as well as other important matrix computations. It uses a coordinate rotation digital computer (CORDIC) module to perform arithmetic operations and several approaches are adopted to achieve high performance including pipelining of the micro-rotations, the use of parallel instructions and a dual-bus architecture. In addition, a novel method for scale factor correction is presented which only needs to be applied once at the end of the computation. This also reduces computation time and enhances performance. Methods are described which allow this processor to be used in reduced dimension (i.e., folded) array processor structures that allow tradeoffs between hardware and performance. The net result is a flexible matrix computational processing element (PE) whose functionality can be changed under program control for use in a wider range of scenarios than previous work. Details are presented of the results of a design study, which considers the application of this decomposition PE architecture in a combined SVD/QRD system and demonstrates that a combination of high performance and efficient silicon implementation are achievable. © 2005 IEEE.