4 resultados para COMPUTER NETWORKS


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Stealthy attackers move patiently through computer networks - taking days, weeks or months to accomplish their objectives in order to avoid detection. As networks scale up in size and speed, monitoring for such attack attempts is increasingly a challenge. This paper presents an efficient monitoring technique for stealthy attacks. It investigates the feasibility of proposed method under number of different test cases and examines how design of the network affects the detection. A methodological way for tracing anonymous stealthy activities to their approximate sources is also presented. The Bayesian fusion along with traffic sampling is employed as a data reduction method. The proposed method has the ability to monitor stealthy activities using 10-20% size sampling rates without degrading the quality of detection.

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Structured parallel programming, and in particular programming models using the algorithmic skeleton or parallel design pattern concepts, are increasingly considered to be the only viable means of supporting effective development of scalable and efficient parallel programs. Structured parallel programming models have been assessed in a number of works in the context of performance. In this paper we consider how the use of structured parallel programming models allows knowledge of the parallel patterns present to be harnessed to address both performance and energy consumption. We consider different features of structured parallel programming that may be leveraged to impact the performance/energy trade-off and we discuss a preliminary set of experiments validating our claims.

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In this paper we advocate the Loop-of-stencil-reduce pattern as a way to simplify the parallel programming of heterogeneous platforms (multicore+GPUs). Loop-of-Stencil-reduce is general enough to subsume map, reduce, map-reduce, stencil, stencil-reduce, and, crucially, their usage in a loop. It transparently targets (by using OpenCL) combinations of CPU cores and GPUs, and it makes it possible to simplify the deployment of a single stencil computation kernel on different GPUs. The paper discusses the implementation of Loop-of-stencil-reduce within the FastFlow parallel framework, considering a simple iterative data-parallel application as running example (Game of Life) and a highly effective parallel filter for visual data restoration to assess performance. Thanks to the high-level design of the Loop-of-stencil-reduce, it was possible to run the filter seamlessly on a multicore machine, on multi-GPUs, and on both.

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This study considers a dual-hop cognitive inter-vehicular relay-assisted communication system where all
communication links are non-line of sight ones and their fading is modelled by the double Rayleigh fading distribution.
Road-side relays (or access points) implementing the decode-and-forward relaying protocol are employed and one of
them is selected according to a predetermined policy to enable communication between vehicles. The performance of
the considered cognitive cooperative system is investigated for Kth best partial and full relay selection (RS) as well as
for two distinct fading scenarios. In the first scenario, all channels are double Rayleigh distributed. In the second
scenario, only the secondary source to relay and relay to destination channels are considered to be subject to double
Rayleigh fading whereas, channels between the secondary transmitters and the primary user are modelled by the
Rayleigh distribution. Exact and approximate expressions for the outage probability performance for all considered RS
policies and fading scenarios are presented. In addition to the analytical results, complementary computer simulated
performance evaluation results have been obtained by means of Monte Carlo simulations. The perfect match between
these two sets of results has verified the accuracy of the proposed mathematical analysis.