Exploiting virtual prototyping for reliability assessment

Products manufactured by the electronics sector are having a major impact in telecommunications, transportation space applications, biomedical applications, consumer products, intelligent hand held devices, and of course,the computer. Demands from end-users in terms of greater product functionality, adoption of environmentally friendly materials, and further miniaturization continually pose several challenges to electronics companies. In the context of electronic product design and manufacture, virtual prototying software tools are allowing companies to dramatically reduce the number of phsysical prototypes and design iterations required in product development and hence reduce costs and time to market. This paper details of the trends in these technolgies and provides an example of their use for flip-chip assembly technology.

Modelling technology to predict flip-chip assembly

This paper describes modelling technology and its use in providing data governing the assembly of flip-chip components. Details are given on the reflow and curing stages as well as the prediction of solder joint shapes. The reflow process involves the attachment of a die to a board via solder joints. After a reflow process, underfill material is placed between the die and the substrate where it is heated and cured. Upon cooling the thermal mismatch between the die, underfill, solder bumps, and substrate will result in a nonuniform deformation profile across the assembly and hence stress. Shape predictions then thermal solidification and stress prediction are undertaken on solder joints during the reflow process. Both thermal and stress calculations are undertaken to predict phenomena occurring during the curing of the underfill material. These stresses may result in delamination between the underfill and its surrounding materials leading to a subsequent reduction in component performance and lifetime. Comparisons between simulations and experiments for die curvature will be given for the reflow and curing process

Virtual manufacturing and design in the real world - implementation and scalability on HPPC systems

Virtual manufacturing and design assessment increasingly involve the simulation of interacting phenomena, sic. multi-physics, an activity which is very computationally intensive. This chapter describes an attempt to address the parallel issues associated with a multi-physics simulation approach based upon a range of compatible procedures operating on one mesh using a single database - the distinct physics solvers can operate separately or coupled on sub-domains of the whole geometric space. Moreover, the finite volume unstructured mesh solvers use different discretization schemes (and, particularly, different ‘nodal’ locations and control volumes). A two-level approach to the parallelization of this simulation software is described: the code is restructured into parallel form on the basis of the mesh partitioning alone, that is, without regard to the physics. However, at run time, the mesh is partitioned to achieve a load balance, by considering the load per node/element across the whole domain. The latter of course is determined by the problem specific physics at a particular location.

The specification and design of an interactive virtual environment for use in teacher training

The original concept was to create a 'simulation' which would provide trainee teachers, specializing in Information and Communications Technology (ICT) with the opportunity to explore a primary school environment. Within the simulation, factors affecting the development and implementation of ICT would be modelled so that trainees would be able to develop the skills, knowledge and understanding necessary to identify appropriate strategies to overcome the limitations. To this end, we have developed Allsorts Primary - the prototype of a simulated interactive environment, representing a typical primary school

Modelling the effect of temperature on product reliability

Reliability of electronic parts is a major concern for many manufacturers, since early failures in the field can cost an enormous amount to repair - in many cases far more than the original cost of the product. A great deal of effort is expended by manufacturers to determine the failure rates for a process or the fraction of parts that will fail in a period of time. It is widely recognized that the traditional approach to reliability predictions for electronic systems are not suitable for today's products. This approach, based on statistical methods only, does not address the physics governing the failure mechanisms in electronic systems. This paper discusses virtual prototyping technologies which can predict the physics taking place and relate this to appropriate failure mechanisms. Simulation results illustrate the effect of temperature on the assembly process of an electronic package and the lifetime of a flip-chip package.

Batching decisions for assembly production systems

The two-stage assembly scheduling problem is a model for production processes that involve the assembly of final or intermediate products from basic components. In our model, there are m machines at the first stage that work in parallel, and each produces a component of a job. When all components of a job are ready, an assembly machine at the second stage completes the job by assembling the components. We study problems with the objective of minimizing the makespan, under two different types of batching that occur in some manufacturing environments. For one type, the time to process a batch on a machine is equal to the maximum of the processing times of its operations. For the other type, the batch processing time is defined as the sum of the processing times of its operations, and a setup time is required on a machine before each batch. For both models, we assume a batch availability policy, i.e., the completion times of the operations in a batch are defined to be equal to the batch completion time. We provide a fairly comprehensive complexity classification of the problems under the first type of batching, and we present a heuristic and its worst-case analysis under the second type of batching.

Using computer models to identify optimal conditions for flip-chip assembly and reliability

Flip-chip assembly, developed in the early 1960s, is now being positioned as a key joining technology to achieve high-density mounting of electronic components on to printed circuit boards for high-volume, low-cost products. Computer models are now being used early within the product design stage to ensure that optimal process conditions are used. These models capture the governing physics taking place during the assembly process and they can also predict relevant defects that may occur. Describes the application of computational modelling techniques that have the ability to predict a range of interacting physical phenomena associated with the manufacturing process. For example, in the flip-chip assembly process we have solder paste deposition, solder joint shape formation, heat transfer, solidification and thermal stress. Illustrates the application of modelling technology being used as part of a larger UK study aiming to establish a process route for high-volume, low-cost, sub-100-micron pitch flip-chip assembly.

Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives

This paper discusses results from a highly interdisciplinary research project which investigated different packaging options for ultra-fine pitch, low temperature and low cost flip-chip assembly. Isotropic Conductive Adhesives (ICAs) are stencil printed to form the interconnects for the package. ICAs are utilized to ensure a low temperature assembly process of flip-chip copper column bumped packages. Results are presented on the structural integrity of novel electroformed stencils. ICA deposits at sub-100 micron pitch and the subsequent thermo-mechanical behaviour of the flip-chip ICA joints are analysed using numerical modelling techniques. Optimal design rules for enhanced performance and thermomechanical reliability of ICA assembled flip-chip packages are formulated.

A modelling and experimental analysis of the no-flow underfill process for flip-chip assembly

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfills as the application and curing of this type of underfill can be undertaken before and during the reflow process - adding high volume throughput. Adopting a no-flow underfill process may result in underfill entrapment between solder and fluid, voiding in the underfill, a possible delamination between underfill and surrounding surfaces. The magnitude of these phenomena may adversely affect the reliability of the assembly in terms of solder joint thermal fatigue. This paper presents both an experimental and mdeling analysis investigating the reliabity of a flip-chip component and how the magnitude of underfill entrapment may affect thermal-mechanical fatigue life.

Powering the virtual university with standard portal technology

This article describes ongoing research on developing a portal framework based on the OASIS Web Services for Remote Portlets (WSRP) standard for integration of Web-based education contents and services made available through a model for a European Networked University. We first identify the requirements for such a framework that supports integration at the presentation level and collaboration in developing and updating study programmes and course materials. We then outline the architecture design, and report on the initial implementation and preliminary evaluation.

Macro-micro modelling of moisture induced stresses in an ACF flip chip assembly

Purpose – This paper discusses the use of modelling techniques to predict the reliability of an anisotropic conductive film (ACF) flip chip in a humid environment. The purpose of this modelling work is to understand the role that moisture plays in the failure of ACF flip chips. Design/methodology/approach – A 3D macro-micro finite element modelling technique was used to determine the moisture diffusion and moisture-induced stresses inside the ACF flip chip. Findings – The results show that the ACF layer in the flip chip can be expected to be fully saturated with moisture after 3?h at 121°C, 100%RH, 2?atm test conditions. The swelling effect of the adhesive due to this moisture absorption causes predominately tensile stress at the interface between the adhesive and the metallization, which could cause a decrease in the contact area, and therefore an increase in the contact resistance. Originality/value – This paper introduces a macro-micro modelling technique which enables more detailed 3D modelling analysis of an ACF flip chip than previously.

Effects of thermal cycling profiles on the performance of chip-on-flex assembly using anisotropic conductive films

Anisotropic conductive films (ACFs) are widely used in the electronic packaging industries because of their fine pitch potential and the assembly process is simpler compared to the soldering process. However, there are still unsolved issues in the volume productions using ACFs. The main reason is that the effects of many factors on the interconnects are not well understood. This work focuses on the performance of ACF-bonded chip-on-flex assemblies subjected to a range of thermal cycling test conditions. Both experimental and three-dimensional finite element computer modelling methods are used. It has been revealed that greater temperature ranges and longer dwell-times give rise to higher stresses in the ACF interconnects. Higher stresses are concentrated along the edges of the chip-ACF interfaces. In the experiments, the results show that higher temperature ranges and prolonged dwell times increase contact resistance values. Close examination of the microstructures along the bond-line through the scanning electron microscope (SEM) indicates that cyclic thermal loads disjoint the conductive particles from the bump of the chip and/or pad of the substrate and this is thought to be related to the increase of the contact resistance value and the failure of the ACF joints.

Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process

This paper presents the results of a packaging process based on the stencil printing of isotropic conductive adhesives (ICAs) that form the interconnections of flip-chip bonded electronic packages. Ultra-fine pitch (sub-100-mum), low temperature (100degC), and low cost flip-chip assembly is demonstrated. The article details recent advances in electroformed stencil manufacturing that use microengineering techniques to enable stencil fabrication at apertures sizes down to 20mum and pitches as small as 30mum. The current state of the art for stencil printing of ICAs and solder paste is limited between 150-mum and 200-mum pitch. The ICAs-based interconnects considered in this article have been stencil printed successfully down to 50-mum pitch with consistent printing demonstrated at 90-mum pitch size. The structural integrity or the stencil after framing and printing is also investigated through experimentation and computational modeling. The assembly of a flip-chip package based on copper column bumped die and ICA deposits stencil printed at sub-100-mum pitch is described. Computational fluid dynamics modeling of the print performance provides an indicator on the optimum print parameters. Finally, an organic light emitting diode display chip is packaged using this assembly process

Recommendations on the nature of the passenger response time distribution to be used in the MSC 1033 assembly time analysis based on data derived from sea trials

The passenger response time distributions adopted by the International Maritime Organisation (IMO)in their assessment of the assembly time for passanger ships involves two key assumptions. The first is that the response time distribution assumes the form of a uniform random distribution and the second concerns the actual response times. These two assumptions are core to the validity of the IMO analysis but are not based on real data, being the recommendations of an IMO committee. In this paper, response time data collected from assembly trials conducted at sea on a real passanger vessel using actual passangers are presented and discussed. Unlike the IMO specified response time distributions, the data collected from these trials displays a log-normal distribution, similar to that found in land based environments. Based on this data, response time distributions for use in the IMO assesmbly for the day and night scenarios are suggested