Performance analysis of a register insertion ring with a variable size buffer

There has been a recent revival of interest in the register insertion (RI) protocol because of its high throughput and low delay characteristics. Several variants of the protocol have been investigated with a view to integrating voice and data applications on a single local area network (LAN). In this paper the performance of an RI ring with a variable size buffer is studied by modelling and simulation. The chief advantage of the proposed scheme is that an efficient but simple bandwidth allocation scheme is easily incorporated. Approximate formulas are derived for queue lengths, queueing times, and total end-to-end transfer delays. The results are compared with previous analyses and with simulation estimates. The effectiveness of the proposed protocol in ensuring fairness of access under conditions of heavy and unequal loading is investigated.

Differential amplifier with improved gain-accuracy and linearity

A novel circuit design technique is presented which improves gain-accuracy and linearity in differential amplifiers. The technique employs negative impedance compensation and results demonstrate a significant performance improvement in precision, lowering sensitivity, and wide dynamic range. A theoretical underpinning is given together with the results of a demonstrator differential input/output amplifier with gain of 12 dB. The simulation results show that, with the novel method, both the gain-accuracy and linearity can be improved greatly. Especially, the linearity improvement in IMD can get to more than 23 dB with a required gain.