Material properties, geometry and their effect on the fatigue life of two flip-chip models

This paper describes how modeling technology has been used in providing fatigue life time data of two flip-chip models. Full-scale three-dimensional modeling of flip-chips under cyclic thermal loading has been combined with solder joint stand-off height prediction to analyze the stress and strain conditions in the two models. The Coffin-Manson empirical relationship is employed to predict the fatigue life times of the solder interconnects. In order to help designers in selecting the underfill material and the printed circuit board, the Young's modulus and the coefficient of thermal expansion of the underfill, as well as the thickness of the printed circuit boards are treated as variable parameters. Fatigue life times are therefore calculated over a range of these material and geometry parameters. In this paper we will also describe how the use of micro-via technology may affect fatigue life

No-flow underfill flip chip assembly–an experimental and modeling analysis

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal–mechanical fatigue life of flip chips with no-flow underfill.

A modelling and experimental analysis of the no-flow underfill process for flip-chip assembly

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfills as the application and curing of this type of underfill can be undertaken before and during the reflow process - adding high volume throughput. Adopting a no-flow underfill process may result in underfill entrapment between solder and fluid, voiding in the underfill, a possible delamination between underfill and surrounding surfaces. The magnitude of these phenomena may adversely affect the reliability of the assembly in terms of solder joint thermal fatigue. This paper presents both an experimental and mdeling analysis investigating the reliabity of a flip-chip component and how the magnitude of underfill entrapment may affect thermal-mechanical fatigue life.

Lifetime assessment of electronic components for high reliability aerospace applications

This paper details a modelling approach for assessing the in-service (field) reliability and thermal fatigue life-time of electronic package interconnects for components used in the assembly of an aerospace system. The Finite Element slice model of a Plastic Ball Grid Array (PBGA) package and suitable energy based damage models for crack length predictions are used in this study. Thermal fatigue damage induced in tin-lead solder joints are investigated by simulating the crack growth process under a set of prescribed field temperature profiles that cover the period of operational life. The overall crack length in the solder joint for all different thermal profiles and number of cycles for each profile is predicted using a superposition technique. The effect of using an underfill is also presented. A procedure for verifying the field lifetime predictions for the electronic package by using reliability assessment under Accelerated Thermal Cycle (ATC) testing is also briefly outlined.

Reliability analysis of SiP structures

This presentation discusses latest developments in SiP technology and the challenges for design in terms of manufacture and reliability. It presents results from a UK government funded project that aims to develop modelling techniques that will assess the thermo-mechanical reliability of SiP structures such as (i) stacked die, (ii) side-by-side dies and (iii) embedded die. Finite element analysis coupled with numerical optimisation and uncertainty analysis is used is used to model the reliability of a particular package design. In particular, the damage (energy density) in the lead free solder interconnects under accelerated temperature cycling is predicted and used to observe the fatigue life-time. Warpage of the structure is also investigated

Computational approach for reliable and robust system-in-package design

A computational modelling approach integrated with optimisation and statistical methods that can aid the development of reliable and robust electronic packages and systems is presented. The design for reliability methodology is demonstrated for the design of a SiP structure. In this study the focus is on the procedure for representing the uncertainties in the package design parameters, their impact on reliability and robustness of the package design and how these can be included in the design optimisation modelling framework. The analysis of thermo-mechanical behaviour of the package is conducted using non-linear transient finite element simulations. Key system responses of interest, the fatigue life-time of the lead-free solder interconnects and warpage of the package, are predicted and used subsequently for design purposes. The design tasks are to identify the optimal SiP designs by varying several package input parameters so that the reliability and the robustness of the package are improved and in the same time specified performance criteria are also satisfied

Reliability based design optimisation for system-in-package

This paper discusses a reliability based optimisation modelling approach demonstrated for the design of a SiP structure integrated by stacking dies one upon the other. In this investigation the focus is on the strategy for handling the uncertainties in the package design inputs and their implementation into the design optimisation modelling framework. The analysis of fhermo-mechanical behaviour of the package is utilised to predict the fatigue life-time of the lead-free board level solder interconnects and warpage of the package under thermal cycling. The SiP characterisation is obtained through the exploitation of Reduced Order Models (ROM) constructed using high fidelity analysis and Design of Experiments (DoE) methods. The design task is to identify the optimal SiP design specification by varying several package input parameters so that a specified target reliability of the solder joints is achieved and in the same time design requirements and package performance criteria are met