Modelling the performance of lead-Free solder interconnects for copper bumped flip-chip devices

Traditionally, before flip chips can be assembled the dies have to be attached with solder bumps. This process involves the deposition of metal layers on the Al pads on the dies and this is called the under bump metallurgy (UBM). In an alternative process, however, Copper (Cu) columns can be used to replace solder bumps and the UBM process may be omitted altogether. After the bumping process, the bumped dies can be assembled on to the printed circuit board (PCB) by using either solder or conductive adhesives. In this work, the reliability issues of flip chips with Cu column bumped dies have been studied. The flip chip lifetime associated with the solder fatigue failure has been modeled for a range of geometric parameters. The relative importance of these parameters is given and solder volume has been identified as the most important design parameter for long-term reliability. Another important problem that has been studied in this work is the dissolution of protection metals on the pad and Cu column in the reflow process. For small solder joints the amount of Cu which dissolves into the molten solder after the protection layers have worn out may significantly affect solder joint properties.

Review of the technology and reliability issues arising as optical interconnects migrate onto the circuit board

Light has the greatest information carrying potential of all the perceivable interconnect mediums; consequently, optical fiber interconnects rapidly replaced copper in telecommunications networks, providing bandwidth capacity far in excess of its predecessors. As a result the modern telecommunications infrastructure has evolved into a global mesh of optical networks with VCSEL’s (Vertical Cavity Surface Emitting Lasers) dominating the short-link markets, predominately due to their low-cost. This cost benefit of VCSELs has allowed optical interconnects to again replace bandwidth limited copper as bottlenecks appear on VSR (Very Short Reach) interconnects between co-located equipment inside the CO (Central-Office). Spurred by the successful deployment in the VSR domain and in response to both intra-board backplane applications and inter-board requirements to extend the bandwidth between IC’s (Integrated Circuits), current research is migrating optical links toward board level USR (Ultra Short Reach) interconnects. Whilst reconfigurable Free Space Optical Interconnect (FSOI) are an option, they are complicated by precise line-of-sight alignment conditions hence benefits exist in developing guided wave technologies, which have been classified into three generations. First and second generation technologies are based upon optical fibers and are both capable of providing a suitable platform for intra-board applications. However, to allow component assembly, an integral requirement for inter-board applications, 3rd generation Opto-Electrical Circuit Boards (OECB’s) containing embedded waveguides are desirable. Currently, the greatest challenge preventing the deployment of OECB’s is achieving the out-of-plane coupling to SMT devices. With the most suitable low-cost platform being to integrate the optics into the OECB manufacturing process, several research avenues are being explored although none to date have demonstrated sufficient coupling performance. Once in place, the OECB assemblies will generate new reliability issues such as assembly configurations, manufacturing tolerances, and hermetic requirements that will also require development before total off-chip photonic interconnection can truly be achieved

Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process

This paper presents the results of a packaging process based on the stencil printing of isotropic conductive adhesives (ICAs) that form the interconnections of flip-chip bonded electronic packages. Ultra-fine pitch (sub-100-mum), low temperature (100degC), and low cost flip-chip assembly is demonstrated. The article details recent advances in electroformed stencil manufacturing that use microengineering techniques to enable stencil fabrication at apertures sizes down to 20mum and pitches as small as 30mum. The current state of the art for stencil printing of ICAs and solder paste is limited between 150-mum and 200-mum pitch. The ICAs-based interconnects considered in this article have been stencil printed successfully down to 50-mum pitch with consistent printing demonstrated at 90-mum pitch size. The structural integrity or the stencil after framing and printing is also investigated through experimentation and computational modeling. The assembly of a flip-chip package based on copper column bumped die and ICA deposits stencil printed at sub-100-mum pitch is described. Computational fluid dynamics modeling of the print performance provides an indicator on the optimum print parameters. Finally, an organic light emitting diode display chip is packaged using this assembly process

A comprehensive copper stockpile leach model: background and model formulation

The first phase in the sign, development and implementation of a comprehensive computational model of a copper stockpile leach process is presented. The model accounts for transport phenomena through the stockpile, reaction kinetics for the important mineral species, oxgen and bacterial effects on the leach reactions, plus heat, energy and acid balances for the overall leach process. The paper describes the formulation of the leach process model and its implementation in PHYSICA+, a computational fluid dynamic (CFD) software environment. The model draws on a number of phenomena to represent the competing physical and chemical features active in the process model. The phenomena are essentially represented by a three-phased (solid liquid gas) multi-component transport system; novel algorithms and procedures are required to solve the model equations, including a methodology for dealing with multiple chemical species with different reaction rates in ore represented by multiple particle size fractions. Some initial validation results and application simulations are shown to illustrate the potential of the model.

A comprehensive copper stockpile leach model: background and parameter sensitivity

The design and development of a comprehensive computational model of a copper stockpile leach process is summarized. The computational fluid dynamic software framework PHYSICA+ and various phenomena were used to model transport phenomena, mineral reaction kinetics, bacterial effects, and heat, energy and acid balances for the overall leach process. In this paper, the performance of the model is investigated, in particular its sensitvity to particle size and ore permeability. A combination of literature and laboratory sources was used to parameterize the model. The simulation results from the leach model are compared with closely controlled column pilot scale tests. The main performance characteristics (e.g. copper recovery rate) predicted by the model compare reasonably well with the experimental data and clearly reflect the qualitiative behavior of the process in many respects. The model is used to provide a measure of the sensitivity of ore permeability on leach behavior, and simulation results are examined for several different particle size distributions.

Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives

This paper discusses results from a highly interdisciplinary research project which investigated different packaging options for ultra-fine pitch, low temperature and low cost flip-chip assembly. Isotropic Conductive Adhesives (ICAs) are stencil printed to form the interconnects for the package. ICAs are utilized to ensure a low temperature assembly process of flip-chip copper column bumped packages. Results are presented on the structural integrity of novel electroformed stencils. ICA deposits at sub-100 micron pitch and the subsequent thermo-mechanical behaviour of the flip-chip ICA joints are analysed using numerical modelling techniques. Optimal design rules for enhanced performance and thermomechanical reliability of ICA assembled flip-chip packages are formulated.

Predicting optimal process conditions for flip-chip aassembly using copper column bumped dies

Recently, research has been carried out to test a novel bumping method which omits the under bump metallurgy (UBM) forming process by bonding copper columns directly onto the Al pads of the silicon dies. This bumping method could be adopted to simplify the flip chip assembly process, increase the productivity and achieve a higher I/O count. Computer modelling methods are used to predict the shape of solder joints and response of the flip chip to thermal cyclic loading. The accumulated plastic strain energy at the comer solder joints is used as the damage indicator. Models with a range of design parameters have been compared for their reliability. The ranking of the relative importance of these parameters is given. Results from these analyses are being used by our industrial and academic partners to identify optimal design conditions.

Predicting the relationship between reliability and geometric parameters of cu column bumped flip-chips

Cu column bumping is a novel flip chip packaging technique that allows Cu columns to be bonded directly with the dies. It has eliminated the under-bump-metallurgy (UBM) fonnation step of the traditional flip chip manufacturing process. This bumping technique has the potential benefits of simplifying the flip chip manufacturing process, increasing productivity and the UO counts. In this paper, a study of reliability of Cu column bumped flip chips will be presented. Computer modelling methods have been used to predict the shape of solder joints and the response of flip chips to cyclic thermal-mechanical loading. The accumulated plastic strain energy at the corner solder joints has been used as an indicator of the solder joint reliability. Models with a wide range of design parameters have been compared for their reliability. The design parameters that have been investigated are the copper column height and radius, PCB pad radius, solder volume and Cu column wetting height. The relative importance ranking of these parameters has been obtained. The Lead-free solder material 96.5Sn3.5Ag has been used in this modelling work.

The effect of curing on the performance of ACF bonded chip-on-flex assemblies after thermal ageing

Purpose – Anisotropic conductive film (ACF) is now an attractive technology for direct mounting of chips onto the substrate as an alternative to lead-free solders. However, despite its various advantages over other technologies, it also has many unresolved reliability issues. For instance, the performance of ACF assembly in high temperature applications is questionable. The purpose of this paper is to study the effect of bonding temperatures on the curing of ACFs, and their mechanical and electrical performance after high temperature ageing. Design/methodology/approach – In the work presented in this paper, the curing degree of an ACF at different bonding temperatures was measured using a differential scanning calorimeter. The adhesion strength and the contact resistance of ACF bonded chip-on-flex assembly were measured before and after thermal ageing and the results were correlated with the curing degree of ACF. The ACF was an epoxy-based adhesive in which Au-Ni coated polymer particles were randomly dispersed. Findings – The results showed that higher bonding temperatures had resulted in better ACF curing and stronger adhesion. After ageing, the adhesion strength increased for the samples bonded at lower temperatures and decreased for the samples bonded at higher temperatures. ACF assemblies with higher degrees of curing showed smaller increases in contact resistance after ageing. Conduction gaps at the bump-particle and/or particle-pad interfaces were found with the help of scanning electron microscopy and are thought to be the root cause of the increase in contact resistance. Originality/value – The present study focuses on the effect of bonding temperatures on the curing of ACFs, and their adhesion strength and electrical performances after high temperature ageing. The results of this study may help the development of ACFs with higher heat resistance, so that ACFs can be considered as an alternative to lead-free solders.

Optimisation modelling for design of advanced interconnects

This paper describes a computational strategy for virtual design and prototyping of electronic components and assemblies. The design process is formulated as a design optimisation problem. The solution of this problem identifies not only the design which meets certain user specified requirements but also the design with the maximum possible improvement in particular aspects such as reliability, cost, etc. The modelling approach exploits numerical techniques for computational analysis (Finite Element Analysis) integrated with numerical methods for approximation, statistical analysis and optimisation. A software framework of modules that incorporates the required numerical techniques is developed and used to carry out the design optimisation modelling of fine-pitch flip-chip lead free solder interconnects.

Effects of thermal cycling profiles on the performance of chip-on-flex assembly using anisotropic conductive films

Anisotropic conductive films (ACFs) are widely used in the electronic packaging industries because of their fine pitch potential and the assembly process is simpler compared to the soldering process. However, there are still unsolved issues in the volume productions using ACFs. The main reason is that the effects of many factors on the interconnects are not well understood. This work focuses on the performance of ACF-bonded chip-on-flex assemblies subjected to a range of thermal cycling test conditions. Both experimental and three-dimensional finite element computer modelling methods are used. It has been revealed that greater temperature ranges and longer dwell-times give rise to higher stresses in the ACF interconnects. Higher stresses are concentrated along the edges of the chip-ACF interfaces. In the experiments, the results show that higher temperature ranges and prolonged dwell times increase contact resistance values. Close examination of the microstructures along the bond-line through the scanning electron microscope (SEM) indicates that cyclic thermal loads disjoint the conductive particles from the bump of the chip and/or pad of the substrate and this is thought to be related to the increase of the contact resistance value and the failure of the ACF joints.

Megasonic agitation for enhanced electrodeposition of copper

In this paper we propose an agitation method based on megasonic acoustic streaming to overcome the limitations in plating rate and uniformity of the metal deposits during the electroplating process. Megasonic agitation at a frequency of 1 MHz allows the reduction of the thickness of the Nernst diffusion layer to less than 600 nm. Two applications that demonstrate the benefits of megasonic acoustic streaming are presented: the formation of uniform ultra-fine pitch flip-chip bumps and the metallisation of high aspect ratio microvias. For the latter application, a multi-physics based numerical simulation is implemented to describe the hydrodynamics introduced by the acoustic waves as they travel inside the deep microvias.

Modeling the diffusion of solid copper into liquid solder alloys

During the soldering process, the copper atoms diffuse into liquid solders. The diffusion process determines integrity and the reworking possibility of a solder joint. In order to capture the diffusion scenarios of solid copper into liquid Sn–Pb and Sn–Cu solders, a computer modeling has been performed for 10 s. An analytical model has also been proposed for calculating the diffusion coefficient of copper into liquid solders. It is found that the diffusion coefficient for Sn–Pb solder is 2.74 × 10− 10 m2/s and for Sn–Cu solder is 6.44 × 10−9 m2/s. The modeling results reveal that the diffusion coefficient is one of the major factors that govern the rate at which solid Cu dissolve in the molten solder. The predicted dissolved amounts of copper into solders have been validated with the help of scanning electron microscopic analysis.

Prooxidant action of knipholone anthrone: Copper dependent reactive oxygen species generation and DNA damage

Knipholone (KP) and knipholone anthrone (KA) are natural 4-phenylanthraquinone structural analogues with established differential biological activities including in vitro antioxidant and cytotoxic properties. By using DNA damage as an experimental model, the comparative Cu(II)-dependent prooxidant action of these two compounds were studied. In the presence of Cu(II) ions, the antioxidant KA (3.1-200 [mu]M) but not KP (6-384 [mu]M) caused a concentration-dependent pBR322 plasmid DNA strand scission. The DNA damage induced by KA could be abolished by reactive oxygen species scavengers, glutathione and catalase as well as EDTA and a specific Cu(I) chelator bathocuproine disulfonic acid. In addition to Cu(II) chelating activity, KA readily reduces Cu(II) to Cu(I). Copper-dependent generation of reactive oxygen species and the subsequent macromolecular damage may be involved in the antimicrobial and cytotoxic activity of KA.