Modelling the behavior of solder joints for wafer level SiP

Design for manufacture of system-in-package (SiP) structures is dependent on a number of physical processes that affect the final quality of the package in terms of its performance and reliability. Solder joints are key structures in a SiP and their behavior can be the critical factor in terms of reliability. This paper discusses the results from a research programme on design for manufacturing of system in package (SiP) technologies. The focus of the paper is on thermo-mechanical modelling of solder joints. This includes the behavior of the joints during testing plus some important insights into the reflow process and how physical phenomena taking place at the assembly stage can affect solder joint behavior. Finite element analysis of a numerical model of an SiP structure with various design parameters is discussed. The goal of this analysis is to identify the most promising combination of design parameters which guarantee longer lifetime of the solder joints and hence the SiP component. The parameters that were studied are the size of the package (i.e. number of solder joints per row), the presence of the underfill and/or the reinforcement as well as the thickness of the passive die. Discussion was also provided on phenomena that take place during the reflow process where the solder joints are formed. In particular, the formation of intermetallics at the solder-pad interfaces

Design for reliability for wafer level system in package

This paper discusses the Design for Reliability modelling of several System-in-Package (SiP) structures developed by NXP and advanced on the basis of Wafer Level Packaging (WLP). Two different types of Wafer Level SiP (WLSiP) are presented and discussed. The main focus is on the modelling approach that has been adopted to investigate and analyse the board level reliability of the presented SiP configurations. Thermo-mechanical non-linear Finite Element Analysis (FEA) is used to analyse the effect of various package design parameters on the reliability of the structures and to identify design trends towards package optimisation. FEA is used also to gain knowledge on moulded wafer shrinkage and related issues during the wafer level fabrication. The paper provides a brief outline and demonstration of a design methodology for reliability driven design optimisation of SiP. The study emphasises the advantages of applying the methodology to address complex design problems where several requirements may exist and uncertainties and interactions between parameters in the design are common.

"System in package technology" - design for manufacture challenges

Purpose – To present key challenges associated with the evolution of system-in-package technologies and present technical work in reliability modeling and embedded test that contributes to these challenges. Design/methodology/approach – Key challenges have been identified from the electronics and integrated MEMS industrial sectors. Solutions to optimising the reliability of a typical assembly process and reducing the cost of production test have been studied through simulation and modelling studies based on technology data released by NXP and in collaboration with EDA tool vendors Coventor and Flomerics. Findings – Characterised models that deliver special and material dependent reliability data that can be used to optimize robustness of SiP assemblies together with results that indicate relative contributions of various structural variables. An initial analytical model for solder ball reliability and a solution for embedding a low cost test for a capacitive RF-MEMS switch identified as an SiP component presenting a key test challenge. Research limitations/implications – Results will contribute to the further development of NXP wafer level system-in-package technology. Limitations are that feedback on the implementation of recommendations and the physical characterisation of the embedded test solution. Originality/value – Both the methodology and associated studies on the structural reliability of an industrial SiP technology are unique. The analytical model for solder ball life is new as is the embedded test solution for the RF-MEMS switch.

Open ended microwave oven for flip-chip assembly

A novel open-ended waveguide cavity resonator for the microwave curing of bumps, underfills and encapsulants is described. The open oven has the potential to provide fast alignment of devices during flip-chip assembly, direct chip attach, surface mount assembly or wafer-scale level packaging. The prototype microwave oven was designed to operate at X-band for ease of testing, although a higher frequency version is planned. The device described in the paper takes the form of a waveguide cavity resonator. It is approximately square in cross-section and is filled with a low-loss dielectric with a relative permittivity of 6. It is excited by end-fed probes in order to couple power preferentially into the TM3,3,k mode with the object of forming nine 'hot-spots' in the open end. Low power tests using heat sensitive film demonstrate clearly that selective heating in multiple locations in the open end of the oven is achievable

Microwave curing for high density package

Summary form only given. Currently the vast majority of adhesive materials in electronic products are bonded using convection heating or infra-red as well as UV-curing. These thermal processing steps can take several hours to perform, slowing throughput and contributing a significant portion of the cost of manufacturing. With the demand for lighter, faster, and smaller electronic devices, there is a need for innovative material processing techniques and control methodologies. The increasing demand for smaller and cheaper devices pose engineering challenges in designing a curing systems that minimize the time required between the curing of devices in a production line, allowing access to the components during curing for alignment and testing. Microwave radiation exhibits several favorable characteristics and over the past few years has attracted increased academic and industrial attention as an alternative solution to curing of flip-chip underfills, bumps, glob top and potting cure, structural bonding, die attach, wafer processing, opto-electronics assembly as well as RF-ID tag bonding. Microwave energy fundamentally accelerates the cure kinetics of polymer adhesives. It provides a route to focus heat into the polymer materials penetrating the substrates that typically remain transparent. Therefore microwave energy can be used to minimise the temperature increase in the surrounding materials. The short path between the energy source and the cured material ensures a rapid heating rate and an overall low thermal budget. In this keynote talk, we will review the principles of microwave curing of materials for high density packing. Emphasis will be placed on recent advances within ongoing research in the UK on the realization of "open-oven" cavities, tailored to address existing challenges. Open-ovens do not require positioning of the device into the cavity through a movable door, hence being more suitable for fully automated processing. Further potential advantages of op- - en-oven curing include the possibility for simultaneous fine placement and curing of the device into a larger assembly. These capabilities promise productivity gains by combining assembly, placement and bonding into a single processing step. Moreover, the proposed design allows for selective heating within a large substrate, which can be useful particularly when the latter includes parts sensitive to increased temperatures.

Open ended microwave oven for packaging

A novel open waveguide cavity resonator is presented for the combined variable frequency microwave curing of bumps, underfills and encapsulants, as well as the alignment of devices for fast flip-chip assembly, direct chip attach (DCA) or wafer-scale level packaging (WSLP). This technology achieves radio frequency (RF) curing of adhesives used in microelectronics, optoelectronics and medical devices with potential simultaneous micron-scale alignment accuracy and bonding of devices. In principle, the open oven cavity can be fitted directly onto a flip-chip or wafer scale bonder and, as such, will allow for the bonding of devices through localised heating thus reducing the risk to thermally sensitive devices. Variable frequency microwave (VFM) heating and curing of an idealised polymer load is numerically simulated using a multi-physics approach. Electro-magnetic fields within a novel open ended microwave oven developed for use in micro-electronics manufacturing applications are solved using a dedicated Yee scheme finite-difference time-domain (FDTD) solver. Temperature distribution, degree of cure and thermal stresses are analysed using an Unstructured Finite Volume method (UFVM) multi-physics package. The polymer load was meshed for thermophysical analysis, whilst the microwave cavity - encompassing the polymer load - was meshed for microwave irradiation. The two solution domains are linked using a cross mapping routine. The principle of heating using the evanescent fringing fields within the open-end of the cavity is demonstrated. A closed loop feedback routine is established allowing the temperature within a lossy sample to be controlled. A distribution of the temperature within the lossy sample is obtained by using a thermal imaging camera.

Investigation of wall-slip effect on paste release characteristic in flip-chip stencil printing process

As the trend toward further miniaturisation of pocket and handheld consumer electronic products continues apace, the requirements for even smaller solder joints will continue. With further reductions in the size of solder joints, the reliability of solder joints will become more and more critical to the long-term performance of electronic products. Solder joints play an important role in electronics packaging, serving both as electrical interconnections between the components and the board, and as mechanical support for components. With world-wide legislation for the removal/reduction of lead and other hazardous materials from electrical and electronic products, the electronics manufacturing industry has been faced with an urgent search for new lead-free solder alloy systems and other solder alternatives. In order to achieve high volume, low cost production, the stencil printing process and subsequent wafer bumping of solder paste has become indispensable. There is wide agreement in industry that the paste printing process accounts for the majority of assembly defects, and most defects originate from poor understanding of the effect of printing process parameters on printing performance. The printing of ICAs and lead-free solder pastes through the very small stencil apertures required for flip chip applications was expected to result in increased stencil clogging and incomplete transfer of paste to the printed circuit pads. Paste release from the stencil apertures is dependent on the interaction between the solder paste, surface pad and aperture wall; including its shape. At these very narrow aperture sizes the paste rheology becomes crucial for consistent paste withdrawal because for smaller paste volumes surface tension effects become dominant over viscous flow. Successful aperture filling and release will greatly depend on the rheology of the paste material. Wall-slip plays an important role in characterising the flow behaviour of solder paste materials. The wall- slip arises due to the various attractive and repulsive forces acting between the solder particles and the walls of the measuring geometry. These interactions could lead to the presence of a thin solvent layer adjacent to the wall, which gives rise to slippage. The wall slip effect can play an important role in ensuring successful paste release after the printing process. The aim of this study was to investigate the influence of the paste microstructure on slip formation for the paste materials (lead-free solder paste and isotropic conductive adhesives). The effect of surface roughness on the paste viscosity was investigated. It was also found that altering the surface roughness of the parallel plate measuring geometry did not significantly eliminate wall slip as was expected. But results indicate that the use of a relatively rough surface helps to increase paste adhesion to the plates, inducing structural breakdown of the paste. Most importantly, the study also demonstrated on how the wall slip formation in the paste material could be utilised for understanding of the paste microstructure and its flow behaviour