Numerical modelling of solder joint formation

Solder materials are used to provide a connection between electronic components and printed circuit boards (PCBs) using either the reflow or wave soldering process. As a board assembly passes through a reflow furnace the solder (initially in the form of solder paste) melts, reflows, then solidifies, and finally deforms between the chip and board. A number of defects may occur during this process such as flux entrapment, void formation, and cracking of the joint, chip or board. These defects are a serious concern to industry, especially with trends towards increasing component miniaturisation and smaller pitch sizes. This paper presents a modelling methodology for predicting solder joint shape, solidification, and deformation (stress) during the assembly process.

Study of the thermal stress in a Pb-free half-bump solder joint under current stressing

The thermal stress in a Sn3.5Ag1Cu half-bump solder joint under a 3.82×108 A/m2 current stressing was analyzed using a coupled-field simulation. Substantial thermal stress accumulated around the Al-to-solder interface, especially in the Ni+(Ni,Cu)3Sn4 layer, where a maximal stress of 138 MPa was identified. The stress gradient in the Ni layer was about 1.67×1013 Pa/m, resulting in a stress migration force of 1.82×10-16 N, which is comparable to the electromigration force, 2.82×10-16 N. Dissolution of the Ni+(Ni,Cu)3Sn4 layer, void formation with cracks at the anode side, and extrusions at the cathode side were observed