A non-Newtonian computational fluid dynamics study of the stencil printing process

This paper describes the application of computational fluid dynamics (CFD) to simulate the macroscopic bulk motion of solder paste ahead of a moving squeegee blade in the stencil printing process during the manufacture of electronic components. The successful outcome of the stencil printing process is dependent on the interaction of numerous process parameters. A better understanding of these parameters is required to determine their relation to print quality and improve guidelines for process optimization. Various modelling techniques have arisen to analyse the flow behaviour of solder paste, including macroscopic studies of the whole mass of paste as well as microstructural analyses of the motion of individual solder particles suspended in the carrier fluid. This work builds on the knowledge gained to date from earlier analytical models and CFD investigations by considering the important non-Newtonian rheological properties of solder pastes which have been neglected in previous macroscopic studies. Pressure and velocity distributions are obtained from both Newtonian and non-Newtonian CFD simulations and evaluated against each other as well as existing established analytical models. Significant differences between the results are observed, which demonstrate the importance of modelling non-Newtonian properties for realistic representation of the flow behaviour of solder paste.

Investigation of wall-slip effect on paste release characteristic in flip-chip stencil printing process

As the trend toward further miniaturisation of pocket and handheld consumer electronic products continues apace, the requirements for even smaller solder joints will continue. With further reductions in the size of solder joints, the reliability of solder joints will become more and more critical to the long-term performance of electronic products. Solder joints play an important role in electronics packaging, serving both as electrical interconnections between the components and the board, and as mechanical support for components. With world-wide legislation for the removal/reduction of lead and other hazardous materials from electrical and electronic products, the electronics manufacturing industry has been faced with an urgent search for new lead-free solder alloy systems and other solder alternatives. In order to achieve high volume, low cost production, the stencil printing process and subsequent wafer bumping of solder paste has become indispensable. There is wide agreement in industry that the paste printing process accounts for the majority of assembly defects, and most defects originate from poor understanding of the effect of printing process parameters on printing performance. The printing of ICAs and lead-free solder pastes through the very small stencil apertures required for flip chip applications was expected to result in increased stencil clogging and incomplete transfer of paste to the printed circuit pads. Paste release from the stencil apertures is dependent on the interaction between the solder paste, surface pad and aperture wall; including its shape. At these very narrow aperture sizes the paste rheology becomes crucial for consistent paste withdrawal because for smaller paste volumes surface tension effects become dominant over viscous flow. Successful aperture filling and release will greatly depend on the rheology of the paste material. Wall-slip plays an important role in characterising the flow behaviour of solder paste materials. The wall- slip arises due to the various attractive and repulsive forces acting between the solder particles and the walls of the measuring geometry. These interactions could lead to the presence of a thin solvent layer adjacent to the wall, which gives rise to slippage. The wall slip effect can play an important role in ensuring successful paste release after the printing process. The aim of this study was to investigate the influence of the paste microstructure on slip formation for the paste materials (lead-free solder paste and isotropic conductive adhesives). The effect of surface roughness on the paste viscosity was investigated. It was also found that altering the surface roughness of the parallel plate measuring geometry did not significantly eliminate wall slip as was expected. But results indicate that the use of a relatively rough surface helps to increase paste adhesion to the plates, inducing structural breakdown of the paste. Most importantly, the study also demonstrated on how the wall slip formation in the paste material could be utilised for understanding of the paste microstructure and its flow behaviour

VCSEL to waveguide coupling for optical backplanes

Hybrid OECB (Opto-Electrical Circuit Boards) are expected to make a significant impact in the telecomm switches arena within the next five years, creating optical backplanes with high speed point-to-point optical interconnects. The critical aspect in the manufacture of the optical backplane is the successful coupling between VCSEL (Vertical Cavity Surface Emitting Laser) device and embedded waveguide in the OECB. Optical performance will be affected by CTE mismatch in the material properties, and manufacturing tolerances. This paper will discuss results from a multidisciplinary research project involving both experimentation and modelling. Key process parameters are being investigated using Design of Experiments and Finite Element Modelling. Simulations have been undertaken that predict the temperature in the VCSEL during normal operation, and the subsequent misalignment that this imposes. The results from the thermomechanical analysis are being used with optimisation software and the experimental DOE (Design of Experiments) to identify packaging parameters that minimise misalignment. These results are also imported into an optical model which solves optical energy and attenuation from the VCSEL aperture into, and then through, the waveguide. Results from the thermomechanical and optical models will be discussed as will the experimental results from the DOE.

Multiscale modelling of dendrite growth during vacuum arc remelting

Vacuum Arc Remelting (VAR) is the accepted method for producing homogeneous, fine microstructures that are free of inclusions required for rotating grade applications. However, as ingot sizes are increasing INCONEL 718 becomes increasingly susceptible to defects such as freckles, tree rings, and white spots increases for large diameter billets. Therefore, predictive models of these defects are required to allow optimization of process parameters. In this paper, a multiscale and multi-physics model is presented to predict the development of microstructures in the VAR ingot during solidification. At the microscale, a combined stochastic nucleation approach and finite difference solution of the solute diffusion is applied in the semi-solid zone of the VAR ingot. The micromodel is coupled with a solution of the macroscale heat transfer, fluid flow and electromagnetism in the VAR process through the temperature, pressure and fluid flow fields. The main objective of this study is to achieve a better understanding of the formation of the defects in VAR by quantifying the influence of VAR processing parameters on grain nucleation and dendrite growth. In particular, the effect of different ingot growth velocities on the microstructure formation was investigated. It was found that reducing the velocity produces significantly more coarse grains.

Optimisation methodology for risk mitigation in advanced micro-system electronics manufacturing

This paper presents a design methodology based on numerical modelling, integrated with optimisation techniques and statistical methods, to aid the development of new advanced technologies in the area of micro and nano systems. The design methodology is demonstrated for a micro-machining process called Focused Ion Beam (FIB). This process has been modelled to provide knowledge of how a pre-defined geometry can be achieved through this direct milling. The geometry characterisation is obtained using a Reduced Order Models (ROM), generated from the results of a mathematical model of the Focused Ion Beam, and Design of Experiment (DoE) methods. In this work, the focus is on the design flow methodology which includes an approach on how to include process parameter uncertainties into the process optimisation modelling framework. A discussion on the impact of the process parameters, and their variations, on the quality and performance of the fabricated structure is also presented. The design task is to identify the optimal process conditions, by altering the process parameters, so that certain reliability and confidence of the application is achieved and the imposed constraints are satisfied. The software tools used and developed to demonstrate the design methodology are also presented.

Minimising the risk of defects in nano-imprint forming

Nano-imprint forming (NIF) is among the most attractive manufacturing technologies offering high yield and low-cost fabrication of three-dimensional fine structures and patterns with resolution of few nanometres. Optimising NIF process is critical for achieving high quality products and minimising the risk of commonly observed defects. Using finite element analysis, the effect of various process parameters is evaluated and design rules for safe and reliable NIF fabrication formulated. This work is part of a major UK Grand Challenge project - 3D-Mintegration - for design, simulation, fabrication, assembly and test of next generation 3D-miniaturised systems.

On variable frequency microwave processing of heterogeneous chip-on-board assemblies

Variable Frequency Microwave (VFM) processing of heterogeneous chip-on-board assemblies is assessed using a multiphysics modelling approach. The Frequency Agile Microwave Oven Bonding System (FAMOBS) is capable of rapidly processing individual packages on a Chip-On-Board (COB) assembly. This enables each package to be processed in an optimal manner, with temperature ramp rate, maximum temperature and process duration tailored to the specific package, a significant benefit in assemblies containing disparate package types. Such heterogeneous assemblies may contain components such as large power modules alongside smaller modules containing low thermal budget materials with highly disparate processing requirements. The analysis of two disparate packages has been assessed numerically to determine the applicability of the dual section microwave system to curing heterogeneous devices and to determine the influence of differing processing requirements of optimal process parameters.

Viscoelastic properties of solder paste and isotropic conductive adhesives used for flip-chip assembly

The printing of pastes (solder pastes and isotropic conductive adhesives) through very small stencil apertures required for flip-chip pitch sizes is expected to result in increased stencil clogging and incomplete transfer of paste to the printed circuit board pads. There is wide agreement in industry that the paste printing process accounts for the majority of assembly defects, and most defects originate from poor understanding of the effect of printing process parameters on printing performance.

The effect of reflow process on the contact resistance and reliability of anisotropic conductive film interconnection for flip chip on flex applications

The work presented in this paper focuses on the effect of reflow process on the contact resistance and reliability of anisotropic conductive film (ACF) interconnection. The contact resistance of ACF interconnection increases after reflow process due to the decrease in contact area of the conducting particles between the mating I/O pads. However, the relationship between the contact resistance and bonding parameters of the ACF interconnection with reflow treatment follows the similar trend to that of the as-bonded (i.e. without reflow) ACF interconnection. The contact resistance increases as the peak temperature of reflow profile increases. Nearly 40% of the joints were found to be open after reflow with 260 °C peak temperature. During the reflow process, the entrapped (between the chip and substrate) adhesive matrix tries to expand much more than the tiny conductive particles because of the higher coefficient of thermal expansion, the induced thermal stress will try to lift the bump from the pad and decrease the contact area of the conductive path and eventually, leading to a complete loss of electrical contact. In addition, the environmental effect on contact resistance such as high temperature/humidity aging test was also investigated. Compared with the ACF interconnections with Ni/Au bump, higher thermal stress in the Z-direction is accumulated in the ACF interconnections with Au bump during the reflow process owing to the higher bump height, thus greater loss of contact area between the particles and I/O pads leads to an increase of contact resistance and poorer reliability after reflow.

Application of CFD in vacuum dezincing process

Most lead bullion is refined by pyrometallurgical methods - this involves a serics of processes that remove the antimony (softening) silver (Parkes process), zinc (vacuum dezincing) and if need be, bismuth (Betterton-Kroll process). The first step, softening, removes the antimony, arsenic and tin by air oxidation in a furnace or by the Harris process. Next, in the Parkes process, zinc is added to the melt to remove the silver and gold. Insoluble zinc, silver and gold compounds are skimmed off from the melt surface. Excess zinc added during desilvering is removed from lead bullion using one of ghree methods: * Vacuum dezincing; * Chlorine dezincing; or * Harris dezincing. The present study concentrates on the Vacuum dezincing process for lead refining. The main aims of the research are to develop mathematical model(s), using Computational Fluid Dyanmics (CFD) a Surface Averaged Model (SAM), to predict the process behaviour under various operating conditions, thus providing detailed information of the process - insight into its reaction to changes of key operating parameters. Finally, the model will be used to optimise the process in terms of initial feed concentration, temperature, vacuum height cooling rate, etc.

Predicting optimal process conditions for flip-chip aassembly using copper column bumped dies

Recently, research has been carried out to test a novel bumping method which omits the under bump metallurgy (UBM) forming process by bonding copper columns directly onto the Al pads of the silicon dies. This bumping method could be adopted to simplify the flip chip assembly process, increase the productivity and achieve a higher I/O count. Computer modelling methods are used to predict the shape of solder joints and response of the flip chip to thermal cyclic loading. The accumulated plastic strain energy at the comer solder joints is used as the damage indicator. Models with a range of design parameters have been compared for their reliability. The ranking of the relative importance of these parameters is given. Results from these analyses are being used by our industrial and academic partners to identify optimal design conditions.

Mathematical modelling: a laser soldering process for an optoelectronics butterfly package

For sensitive optoelectronic components, traditional soldering techniques cannot be used because of their inherent sensitivity to thermal stresses. One such component is the Optoelectronic Butterfly Package which houses a laser diode chip aligned to a fibre-optic cable. Even sub-micron misalignment of the fibre optic and laser diode chip can significantly reduce the performance of the device. The high cost of each unit requires that the number of damaged components, via the laser soldering process, are kept to a minimum. Mathematical modelling is undertaken to better understand the laser soldering process and to optimize operational parameters such as solder paste volume, copper pad dimensions, laser solder times for each joint, laser intensity and absorption coefficient. Validation of the model against experimental data will be completed, and will lead to an optimization of the assembly process, through an iterative modelling cycle. This will ultimately reduce costs, improve the process development time and increase consistency in the laser soldering process.

Predicting the relationship between reliability and geometric parameters of cu column bumped flip-chips

Cu column bumping is a novel flip chip packaging technique that allows Cu columns to be bonded directly with the dies. It has eliminated the under-bump-metallurgy (UBM) fonnation step of the traditional flip chip manufacturing process. This bumping technique has the potential benefits of simplifying the flip chip manufacturing process, increasing productivity and the UO counts. In this paper, a study of reliability of Cu column bumped flip chips will be presented. Computer modelling methods have been used to predict the shape of solder joints and the response of flip chips to cyclic thermal-mechanical loading. The accumulated plastic strain energy at the corner solder joints has been used as an indicator of the solder joint reliability. Models with a wide range of design parameters have been compared for their reliability. The design parameters that have been investigated are the copper column height and radius, PCB pad radius, solder volume and Cu column wetting height. The relative importance ranking of these parameters has been obtained. The Lead-free solder material 96.5Sn3.5Ag has been used in this modelling work.

Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process

This paper presents the results of a packaging process based on the stencil printing of isotropic conductive adhesives (ICAs) that form the interconnections of flip-chip bonded electronic packages. Ultra-fine pitch (sub-100-mum), low temperature (100degC), and low cost flip-chip assembly is demonstrated. The article details recent advances in electroformed stencil manufacturing that use microengineering techniques to enable stencil fabrication at apertures sizes down to 20mum and pitches as small as 30mum. The current state of the art for stencil printing of ICAs and solder paste is limited between 150-mum and 200-mum pitch. The ICAs-based interconnects considered in this article have been stencil printed successfully down to 50-mum pitch with consistent printing demonstrated at 90-mum pitch size. The structural integrity or the stencil after framing and printing is also investigated through experimentation and computational modeling. The assembly of a flip-chip package based on copper column bumped die and ICA deposits stencil printed at sub-100-mum pitch is described. Computational fluid dynamics modeling of the print performance provides an indicator on the optimum print parameters. Finally, an organic light emitting diode display chip is packaged using this assembly process