Variable frequency microwave curing of polymer materials in microelectronics packaging applications

The use of variable frequency microwave technology in curing of polymer materials used in microelectronics applications is discussed. A revolutionary open-ended microwave curing system is outlined and assessed using experimental and numerical approaches. Experimental and numerical results are presented, demonstrating the feasibility of the system

Multi-physics modelling for microelectronics and microsystems - current capabilities and future challenges

At present the vast majority of Computer-Aided- Engineering (CAE) analysis calculations for microelectronic and microsystems technologies are undertaken using software tools that focus on single aspects of the physics taking place. For example, the design engineer may use one code to predict the airflow and thermal behavior of an electronic package, then another code to predict the stress in solder joints, and then yet another code to predict electromagnetic radiation throughout the system. The reason for this focus of mesh-based codes on separate parts of the governing physics is essentially due to the numerical technologies used to solve the partial differential equations, combined with the subsequent heritage structure in the software codes. Using different software tools, that each requires model build and meshing, leads to a large investment in time, and hence cost, to undertake each of the simulations. During the last ten years there has been significant developments in the modelling community around multi- physics analysis. These developments are being followed by many of the code vendors who are now providing multi-physics capabilities in their software tools. This paper illustrates current capabilities of multi-physics technology and highlights some of the future challenges

Optimization of an open-ended microwave oven for microelectronics packaging

A physically open, but electrically shielded, microwave open oven can be produced by virtue of the evanescent fields in a waveguide below cutoff. The below cutoff heating chamber is fed by a transverse magnetic resonance established in a dielectric-filled section of the waveguide exploiting continuity of normal electric flux. In order to optimize the fields and the performance of the oven, a thin layer of a dielectric material with higher permittivity is inserted at the interface. Analysis and synthesis of an optimized open oven predicts field enhancement in the heating chamber up to 9.4 dB. Results from experimental testing on two fabricated prototypes are in agreement with the simulated predictions, and demonstrate an up to tenfold improvement in the heating performance. The open-ended oven allows for simultaneous precision alignment, testing, and efficient curing of microelectronic devices, significantly increasing productivity gains.

Polymer cure modeling for microelectronics applications

A review of polymer cure models used in microelectronics packaging applications reveals no clear consensus of the chemical rate constants for the cure reactions, or even of an effective model. The problem lies in the contrast between the actual cure process, which involves a sequence of distinct chemical reactions, and the models, which typically assume only one, (or two with some restrictions on the independence of their characteristic constants.) The standard techniques to determine the model parameters are based on differential scanning calorimetry (DSC), which cannot distinguish between the reactions, and hence yields results useful only under the same conditions, which completely misses the point of modeling. The obvious solution is for manufacturers to provide the modeling parameters, but failing that, an alternative experimental technique is required to determine individual reaction parameters, e.g. Fourier transform infra-red spectroscopy (FTIR).

A critical analysis of polymer cure modeling for microelectronics applications

A review of polymer cure models used in microelectronics packaging applications reveals no clear consensus of the chemical rate constants for the cure reactions, or even of an effective model. The problem lies in the contrast between the actual cure process, which involves a sequence of distinct chemical reactions, and the models, which typically assume only one, (or two with some restrictions on the independence of their characteristic constants.) The standard techniques to determine the model parameters are based on differential scanning calorimetry (DSC), which cannot distinguish between the reactions, and hence yields results useful only under the same conditions, which completely misses the point of modeling. The obvious solution is for manufacturers to provide the modeling parameters, but failing that, an alternative experimental technique is required to determine individual reaction parameters, e.g. Fourier transform infra-red spectroscopy (FTIR).

Microwave curing of thermosetting polymer materials in microelectronics applications

Thermosetting polymer materials are widely utilised in modern microelectronics packaging technology. These materials are used for a number of functions, such as for device bonding, for structural support applications and for physical protection of semiconductor dies. Typically, convection heating systems are used to raise the temperature of the materials to expedite the polymerisation process. The convection cure process has a number of drawbacks including process durations generally in excess of 1 hour and the requirement to heat the entire printed circuit board assembly, inducing thermomechanical stresses which effect device reliability. Microwave energy is able to raise the temperature of materials in a rapid, controlled manner. As the microwave energy penetrates into the polymer materials, the heating can be considered volumetric – i.e. the rate of heating is approximately constant throughout the material. This enables a maximal heating rate far greater than is available with convection oven systems which only raise the surface temperature of the polymer material and rely on thermal conductivity to transfer heat energy into the bulk. The high heating rate, combined with the ability to vary the operating power of the microwave system, enables the extremely rapid cure processes. Microwave curing of a commercially available encapsulation material has been studied experimentally and through use of numerical modelling techniques. The material assessed is Henkel EO-1080, a single component thermosetting epoxy. The producer has suggested three typical convection oven cure options for EO1080: 20 min at 150C or 90 min at 140C or 120 min at 110C. Rapid curing of materials of this type using advanced microwave systems, such as the FAMOBS system [1], is of great interest to microelectronics system manufacturers as it has the potential to reduce manufacturing costs, increase device reliability and enables new device designs. Experimental analysis has demonstrated that, in a realistic chip-on-board encapsulation scenario, the polymer material can be fully cured in approximately one minute. This corresponds to a reduction in cure time of approximately 95 percent relative to the convection oven process. Numerical assessment of the process [2] also suggests that cure times of approximately 70 seconds are feasible whilst indicating that the decrease in process duration comes at the expense of variation in degree of cure within the polymer.

The effect of reflow process on the contact resistance and reliability of anisotropic conductive film interconnection for flip chip on flex applications

The work presented in this paper focuses on the effect of reflow process on the contact resistance and reliability of anisotropic conductive film (ACF) interconnection. The contact resistance of ACF interconnection increases after reflow process due to the decrease in contact area of the conducting particles between the mating I/O pads. However, the relationship between the contact resistance and bonding parameters of the ACF interconnection with reflow treatment follows the similar trend to that of the as-bonded (i.e. without reflow) ACF interconnection. The contact resistance increases as the peak temperature of reflow profile increases. Nearly 40% of the joints were found to be open after reflow with 260 °C peak temperature. During the reflow process, the entrapped (between the chip and substrate) adhesive matrix tries to expand much more than the tiny conductive particles because of the higher coefficient of thermal expansion, the induced thermal stress will try to lift the bump from the pad and decrease the contact area of the conductive path and eventually, leading to a complete loss of electrical contact. In addition, the environmental effect on contact resistance such as high temperature/humidity aging test was also investigated. Compared with the ACF interconnections with Ni/Au bump, higher thermal stress in the Z-direction is accumulated in the ACF interconnections with Au bump during the reflow process owing to the higher bump height, thus greater loss of contact area between the particles and I/O pads leads to an increase of contact resistance and poorer reliability after reflow.

No-flow underfill flip chip assembly–an experimental and modeling analysis

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal–mechanical fatigue life of flip chips with no-flow underfill.

Finite element modelling of crack detection tests

Four non-destructive tests for determining the length of fatigue cracks within the solder joints of a 2512 surface mount resistor are investigated. The sensitivity of the tests is obtained using finite element analysis with some experimental validation. Three of the tests are mechanically based and one is thermally based. The mechanical tests all operate by applying different loads to the PCB and monitoring the strain response at the top of the resistor. The thermal test operates by applying a heat source underneath the PCB, and monitoring the temperature response at the top of the resistor. From the modelling work done, two of these tests have shown to be sensitive to cracks. Some experimental results are presented but further work is required to fully validate the simulation results.

Polymer waveguide and VCSEL array multi-physics modelling for OECB based optical backplanes [opto-electrical circuit boards]

The deployment of OECBs (opto-electrical circuit boards) is expected to make a significant impact in the telecomm switches arena within the next five years. This will create optical backplanes with high speed point-to-point optical interconnects. The crucial aspect in the manufacturing process of the optical backplane is the successful coupling between VCSEL (vertical cavity surface emitting laser) device and embedded waveguide in the OECB. The results from a thermo-mechanical analysis are being used in a purely optical model, which solves optical energy and attenuation from the VCSEL aperture into, and then through, the waveguide. Results from the modelling are being investigated using DOE analysis to identify packaging parameters that minimise misalignment. This is achieved via a specialist optimisation software package. Results from the thermomechanical and optical models are discussed as are experimental results from the DOE.

Low Reynolds number turbulence models for accurate thermal simulations of electronic components

The electronics industry and the problems associated with the cooling of microelectronic equipment are developing rapidly. Thermal engineers now find it necessary to consider the complex area of equipment cooling at some level. This continually growing industry also faces heightened pressure from consumers to provide electronic product miniaturization, which in itself increases the demand for accurate thermal management predictions to assure product reliability. Computational fluid dynamics (CFD) is considered a powerful and almost essential tool for the design, development and optimization of engineering applications. CFD is now widely used within the electronics packaging design community to thermally characterize the performance of both the electronic component and system environment. This paper discusses CFD results for a large variety of investigated turbulence models. Comparison against experimental data illustrates the predictive accuracy of currently used models and highlights the growing demand for greater mathematical modelling accuracy with regards to thermal characterization. Also a newly formulated low Reynolds number (i.e. transitional) turbulence model is proposed with emphasis on hybrid techniques.

Study of Anisotropic Conductive Adhesive Joint Behaviour under 3-Point Bending

Flip chip interconnections using anisotropic conductive film (ACF) are now a very attractive technique for electronic packaging assembly. Although ACF is environmentally friendly, many factors may influence the reliability of the final ACF joint. External mechanical loading is one of these factors. Finite element analysis (FEA) was carried out to understand the effect of mechanical loading on the ACF joint. A 3-dimensional model of adhesively bonded flip chip assembly was built and simulations were performed for the 3-point bending test. The results show that the stress at its highest value at the corners, where the chip and ACF were connected together. The ACF thickness was increased at these corner regions. It was found that higher mechanical loading results in higher stress that causes a greater gap between the chip and the substrate at the corner position. Experimental work was also carried out to study the electrical reliability of the ACF joint with the applied bending load. As per the prediction from FEA, it was found that at first the corner joint failed. Successive open joints from the corner towards the middle were also noticed with the increase of the applied load.

Computational modelling for reliable flip-chip packaging at sub-100 micron pitch using isotropic conductive adhesives

This paper presents the assembly process using next generation electroformed stencils and Isotropic Conductive Adhesives (ICAs) as interconnection material. The utilisation of ICAs in flip-chip assembly process is investigated as an alternative to the lead and lead-free solder alloys and aims to ensure a low temperature (T < 100 °C) assembly process. The paper emphasizes and discusses in details the assembly of a flip-chip package based on copper columns bumped die and substrate with stencil printed ICA deposits at sub-100 μm pitch. A computational modelling approach is undertaken to provide comprehensive results on reliability trends of ICA joints subject to thermal cycling of the flip-chip assembly based on easy to use damage criteria and damage evaluation. Important design parameters in the package are selected and investigated using numerical modelling techniques to provide knowledge and understanding of their impact on the thermo-mechanical behaviour of the flip-chip ICA joints. Sensitivity analysis of the damage in the adhesive material is also carried out. Optimal design rules for enhanced performance and improved thermo-mechanical reliability of ICA assembled flip-chip packages are finally formulated.

Assessing the performance of crack detection tests for solder joints

This paper presents both modelling and experimental test data to characterise the performance of four non-destructive tests. The focus is on determining the presence and rough magnitude of thermal fatigue cracks within the solder joints for a surface mount resistor on a strip of FR4 PCB. The tests all operate by applying mechanical loads to the PCB and monitoring the strain response at the top of the resistor. The modelling results show that of the four tests investigated, three are sensitive to the presence of a crack in the joint and its magnitude. Hence these tests show promise in being able to detect cracking caused by accelerated testing. The experimental data supports these results although more validation is required.

Reliability study of the electroless Ni–P layer against solder alloy

Copper (Cu) has been widely used in the under bump metallurgy of chip and substrate metallization for chip packaging. However, due to the rapid formation of Cu–Sn intermetallic compound (IMC) at the tin-based solder/Cu interface during solder reaction, the reliability of this type of solder joint is a serious concern. In this work, electroless nickel–phosphorous (Ni–P) layer was deposited on the Cu pad of the flexible substrate as a diffusion barrier between Cu and the solder materials. The deposition was carried out in a commercial acidic sodium hypophosphite bath at 85 °C for different pH values. It was found that for the same deposition time period, higher pH bath composition (mild acidic) yields thicker Ni–P layer with lower phosphorous content. Solder balls having composition 62%Sn–36%Pb–2%Ag were reflowed at 240 °C for 1 to 180 min on three types of electroless Ni–P layers deposited at the pH value of 4, 4.8 and 6, respectively. Thermal stability of the electroless Ni–P barrier layer against the Sn–36%Pb–2%Ag solder reflowed for different time periods was examined by scanning electron microscopy equipped with energy dispersed X-ray. Solder ball shear test was performed in order to find out the relationship between the mechanical strength of solder joints and the characteristics of the electroless Ni–P layer deposited. The layer deposited in the pH 4 acidic bath showed the weak barrier against reflow soldering whereas layer deposited in pH 6 acidic bath showed better barrier against reflow soldering. Mechanical strength of the joints were deteriorated quickly in the layer deposited at pH 4 acidic bath, which was found to be thin and has a high phosphorous content. From the cross-sectional studies and fracture surface analyses, it was found that the appearance of the dark crystalline phosphorous-rich Ni layer weakened the interface and hence lower solder ball shear strength. Ni–Sn IMC formed at the interfaces was found to be more stable at the low phosphorous content (∼14 at.%) layer. Electroless Ni–P deposited at mild acidic bath resulting phosphorous content of around 14 at.% is suggested as the best barrier layer for Sn–36%Pb–2%Ag solder.