38 resultados para Layout (Printing)

em Greenwich Academic Literature Archive - UK


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This paper describes the application of computational fluid dynamics (CFD) to simulate the macroscopic bulk motion of solder paste ahead of a moving squeegee blade in the stencil printing process during the manufacture of electronic components. The successful outcome of the stencil printing process is dependent on the interaction of numerous process parameters. A better understanding of these parameters is required to determine their relation to print quality and improve guidelines for process optimization. Various modelling techniques have arisen to analyse the flow behaviour of solder paste, including macroscopic studies of the whole mass of paste as well as microstructural analyses of the motion of individual solder particles suspended in the carrier fluid. This work builds on the knowledge gained to date from earlier analytical models and CFD investigations by considering the important non-Newtonian rheological properties of solder pastes which have been neglected in previous macroscopic studies. Pressure and velocity distributions are obtained from both Newtonian and non-Newtonian CFD simulations and evaluated against each other as well as existing established analytical models. Significant differences between the results are observed, which demonstrate the importance of modelling non-Newtonian properties for realistic representation of the flow behaviour of solder paste.

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Soldering technologies continue to evolve to meet the demands of the continuous miniaturisation of electronic products, particularly in the area of solder paste formulations used in the reflow soldering of surface mount devices. Stencil printing continues to be a leading process used for the deposition of solder paste onto printed circuit boards (PCBs) in the volume production of electronic assemblies, despite problems in achieving a consistent print quality at an ultra-fine pitch. In order to eliminate these defects a good understanding of the processes involved in printing is important. Computational simulations may complement experimental print trials and paste characterisation studies, and provide an extra dimension to the understanding of the process. The characteristics and flow properties of solder pastes depend primarily on their chemical and physical composition and good material property data is essential for meaningful results to be obtained by computational simulation.This paper describes paste characterisation and computational simulation studies that have been undertaken through the collaboration of the School of Aeronautical, Mechanical and Manufacturing Engineering at Salford University and the Centre for Numerical Modelling and Process Analysis at the University of Greenwich. The rheological profile of two different paste formulations (lead and lead-free) for sub 100 micron flip-chip devices are tested and applied to computational simulations of their flow behaviour during the printing process.

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This article presents the latest print results at less than 100 microns pitch obtained in stencil printing type 6 and 7 lead-free solder pastes and conductive adhesives. The advantages of the microengineered stencil arc presented and compared with other bonding technologies. Characterisation of the print deposits is presented and future applications of stencil printing are described.

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This article presents the latest print results at less than 100 microns pitch obtained in stencil printing type 6 and 7 leadfree solder pastes and conductive adhesives. The advantages of the microengineered stencil are presented and compared with other bonding technologies. Characterisation of the print deposits is presented and future applications of stencil printing are described.

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This paper presents the results of a packaging process based on the stencil printing of isotropic conductive adhesives (ICAs) that form the interconnections of flip-chip bonded electronic packages. Ultra-fine pitch (sub-100-mum), low temperature (100degC), and low cost flip-chip assembly is demonstrated. The article details recent advances in electroformed stencil manufacturing that use microengineering techniques to enable stencil fabrication at apertures sizes down to 20mum and pitches as small as 30mum. The current state of the art for stencil printing of ICAs and solder paste is limited between 150-mum and 200-mum pitch. The ICAs-based interconnects considered in this article have been stencil printed successfully down to 50-mum pitch with consistent printing demonstrated at 90-mum pitch size. The structural integrity or the stencil after framing and printing is also investigated through experimentation and computational modeling. The assembly of a flip-chip package based on copper column bumped die and ICA deposits stencil printed at sub-100-mum pitch is described. Computational fluid dynamics modeling of the print performance provides an indicator on the optimum print parameters. Finally, an organic light emitting diode display chip is packaged using this assembly process

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Lead-free solder paste printing process accounts for majority of the assembly defects in the electronic manufacturing industry. The study investigates rheological behaviour and stencil printing performance of the lead-free solder pastes (Sn/Ag/Cu). Oscillatory stress sweep test was carried out to study the visco-elastic behaviour of the lead-free solder pastes. The visco-elastic behaviour of the paste encompasses solid and liquid characteristic of the paste, which could be used to study the flow behaviour experienced by the pastes during the stencil printing process. From this study, it was found that the solid characteristics (G0) is higher than the liquid characteristic (G0 0) for the pastes material. In addition, the results from the study showed that the solder paste with a large G0 = G0 0 has a higher cohesiveness resulting in poor withdrawal of the paste during the stencil printing process. The phase angles (d) was used to correlate the quality of the dense suspensions to the formulation of solder paste materials. This study has revealed the value of having a rheological measurement for explaining and characterising solder pastes for stencil printing. As the demand for lead free pastes increases rheological measurements can assist with the formulation or development of new pastes.

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Solder paste plays an important role in the electronic assembly process by providing electrical, mechanical and thermal bonding between the components and the substrate. The rheological characterisation of pastes is an important step in the design and development of new paste formulations. With the ever increasing trend of miniaturisation of electronic products, the study of the rheological properties of solder pastes is becoming an integral part in the R&D of new paste formulations and in the quality monitoring and control during paste manufacture and electronic assembly process. This research work outlines some of the novel techniques which can be successfully used to investigate the rheology of leadfree solder pastes. The report also presents the results of the correlation of rheological properties with solder paste printing performance. Four different solder paste samples (namely paste P1, P2, P3 and P4) with different flux vehicle systems and particle size distributions were investigated in the study. As expected, all the paste samples showed shear thinning behaviour. Although the samples displayed similar flow behaviour at high shear rates, differences were observed at low shear rates. In the stencil printing trials, round deposits showed better results than rectangular deposits in terms of paste heights and aperture filling. Our results demonstrate a good correlation between higher paste viscosity and good printing performance. The results of the oscillatory and thixotropy tests were also successfully correlated to the printing behaviour of solder paste.

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Evaluating ship layout for human factors (HF) issues using simulation software such as maritimeEXODUS can be a long and complex process. The analysis requires the identification of relevant evaluation scenarios; encompassing evacuation and normal operations; the development of appropriate measures which can be used to gauge the performance of crew and vessel and finally; the interpretation of considerable simulation data. In this paper we present a systematic and transparent methodology for assessing the HF performance of ship design which is both discriminating and diagnostic.

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As the trend toward further miniaturisation of pocket and handheld consumer electronic products continues apace, the requirements for even smaller solder joints will continue. With further reductions in the size of solder joints, the reliability of solder joints will become more and more critical to the long-term performance of electronic products. Solder joints play an important role in electronics packaging, serving both as electrical interconnections between the components and the board, and as mechanical support for components. With world-wide legislation for the removal/reduction of lead and other hazardous materials from electrical and electronic products, the electronics manufacturing industry has been faced with an urgent search for new lead-free solder alloy systems and other solder alternatives. In order to achieve high volume, low cost production, the stencil printing process and subsequent wafer bumping of solder paste has become indispensable. There is wide agreement in industry that the paste printing process accounts for the majority of assembly defects, and most defects originate from poor understanding of the effect of printing process parameters on printing performance. The printing of ICAs and lead-free solder pastes through the very small stencil apertures required for flip chip applications was expected to result in increased stencil clogging and incomplete transfer of paste to the printed circuit pads. Paste release from the stencil apertures is dependent on the interaction between the solder paste, surface pad and aperture wall; including its shape. At these very narrow aperture sizes the paste rheology becomes crucial for consistent paste withdrawal because for smaller paste volumes surface tension effects become dominant over viscous flow. Successful aperture filling and release will greatly depend on the rheology of the paste material. Wall-slip plays an important role in characterising the flow behaviour of solder paste materials. The wall- slip arises due to the various attractive and repulsive forces acting between the solder particles and the walls of the measuring geometry. These interactions could lead to the presence of a thin solvent layer adjacent to the wall, which gives rise to slippage. The wall slip effect can play an important role in ensuring successful paste release after the printing process. The aim of this study was to investigate the influence of the paste microstructure on slip formation for the paste materials (lead-free solder paste and isotropic conductive adhesives). The effect of surface roughness on the paste viscosity was investigated. It was also found that altering the surface roughness of the parallel plate measuring geometry did not significantly eliminate wall slip as was expected. But results indicate that the use of a relatively rough surface helps to increase paste adhesion to the plates, inducing structural breakdown of the paste. Most importantly, the study also demonstrated on how the wall slip formation in the paste material could be utilised for understanding of the paste microstructure and its flow behaviour

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Stencil printing of solder pastes is a critical stage in the SMT assembly process as a high proportion of the solder-related defects can be attributed to this stage. As the trend towards product miniaturization continues, there is a greater need for better understanding of the rheological behaviour and printing performance of new paste formulations. This fundamental understanding is crucial for achieving the repeatable solder paste deposits from board-to-board and pad-to-pad required for more reliable solder interconnections. The paper concerns a study on the effect of ageing on the rheological characteristics and printing performance of new lead-free solder pastes formulations used for flip-chip assembly applications. The objective is to correlate the rheological characteristics of aged paste samples to their printing performance. The methodology developed can be used for bench-marking new lead-free paste formulations in terms of shelf life, the potential deterioration in rheological characteristics and their printing performance.

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We describe a heuristic method for drawing graphs which uses a multilevel technique combined with a force-directed placement algorithm. The multilevel process groups vertices to form clusters, uses the clusters to define a new graph and is repeated until the graph size falls below some threshold. The coarsest graph is then given an initial layout and the layout is successively refined on all the graphs starting with the coarsest and ending with the original. In this way the multilevel algorithm both accelerates and gives a more global quality to the force- directed placement. The algorithm can compute both 2 & 3 dimensional layouts and we demonstrate it on a number of examples ranging from 500 to 225,000 vertices. It is also very fast and can compute a 2D layout of a sparse graph in around 30 seconds for a 10,000 vertex graph to around 10 minutes for the largest graph. This is an order of magnitude faster than recent implementations of force-directed placement algorithms.

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We describe a heuristic method for drawing graphs which uses a multilevel framework combined with a force-directed placement algorithm. The multilevel technique matches and coalesces pairs of adjacent vertices to define a new graph and is repeated recursively to create a hierarchy of increasingly coarse graphs, G0, G1, …, GL. The coarsest graph, GL, is then given an initial layout and the layout is refined and extended to all the graphs starting with the coarsest and ending with the original. At each successive change of level, l, the initial layout for Gl is taken from its coarser and smaller child graph, Gl+1, and refined using force-directed placement. In this way the multilevel framework both accelerates and appears to give a more global quality to the drawing. The algorithm can compute both 2 & 3 dimensional layouts and we demonstrate it on examples ranging in size from 10 to 225,000 vertices. It is also very fast and can compute a 2D layout of a sparse graph in around 12 seconds for a 10,000 vertex graph to around 5-7 minutes for the largest graphs. This is an order of magnitude faster than recent implementations of force-directed placement algorithms.

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The newly formed Escape and Evacuation Naval Authority regulates the provision of abandonment equipment and procedures for all Ministry of Defence Vessels. As such, it assures that access routes on board are evaluated early in the design process to maximize their efficiency and to eliminate, as far as possible, any congestion that might occur during escape. This analysis can be undertaken using a computer-based simulation for given escape scenarios and replicates the layout of the vessel and the interactions between each individual and the ship structure. One such software tool that facilitates this type of analysis is maritimeEXODUS. This tool, through large scale testing and validation, emulates human shipboard behaviour during emergency scenarios; however it is largely based around the behaviour of civilian passengers and fixtures and fittings of merchant vessels. Hence there existed a clear requirement to understand the behaviour of well-trained naval personnel as opposed to civilian passengers and be able to model the fixtures and fittings that are exclusive to warships, thus allowing improvements to both maritimeEXODUS and other software products. Human factor trials using the Royal Navy training facilities at Whale Island, Portsmouth were recently undertaken to collect data that improves our understanding of the aforementioned differences. It is hoped that this data will form the basis of a long-term improvement package that will provide global validation of these simulation tools and assist in the development of specific Escape and Evacuation standards for warships. © 2005: Royal Institution of Naval Architects.

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Occupant interaction with signage systems is being introduced into evacuation simulations through the newly developed concept of the Visibility Catchment Area or VCA. In this article, we describe the concept of VCA and how it has been extended to incorporate the presence of physical obstructions and termination distance. The VCA concept is then linked to a prototype behavior model intended to represent the occupant's interaction with the signage system. The functionality and performance of the newly developed model is then demonstrated through the simulation of various evacuation scenarios within a hypothetical supermarket layout