105 resultados para Eutectic Solder
Resumo:
Experiments as well as computer modeling methods have been used to investigate the effect of the solder reflow process on the electrical characteristics and reliability of anisotropic conductive film (ACF) interconnections. In the experiments, the contact resistance of the ACF interconnections was found to increase after a subsequent reflow and the magnitude of this increase was strongly correlated to the peak temperature of the reflow profile. In fact, nearly 40 percent of the joints were opened (i.e. lifted away from the pad) after the reflow with a peak temperature of 260 OC while no openings was observed when the peak temperature was 210 "C. It is believed that the CTE mismatch between the polymer particle and the adhesive matrix is the main cause of this contact degradation. To understand this phenomenon better, a 3-D model of an ACF joint structure was built and Finite Element Analysis was used to predict the stress distrihution in the conductive particles, adhesive matrix and metal pads during the reflow process. The effects of the peak temperature, the CTE of the adhesive matrix and the bump height on the reliability of the ACF interconnections were discussed.
Resumo:
Traditionally, before flip chips can be assembled the dies have to be attached with solder bumps. This process involves the deposition of metal layers on the Al pads on the dies and this is called the under bump metallurgy (UBM). In an alternative process, however, Copper (Cu) columns can be used to replace solder bumps and the UBM process may be omitted altogether. After the bumping process, the bumped dies can be assembled on to the printed circuit board (PCB) by using either solder or conductive adhesives. In this work, the reliability issues of flip chips with Cu column bumped dies have been studied. The flip chip lifetime associated with the solder fatigue failure has been modeled for a range of geometric parameters. The relative importance of these parameters is given and solder volume has been identified as the most important design parameter for long-term reliability. Another important problem that has been studied in this work is the dissolution of protection metals on the pad and Cu column in the reflow process. For small solder joints the amount of Cu which dissolves into the molten solder after the protection layers have worn out may significantly affect solder joint properties.
Resumo:
The future success of many electronics companies will depend to a large extent on their ability to initiate techniques that bring schedules, performance, tests, support, production, life-cycle-costs, reliability prediction and quality control into the earliest stages of the product creation process. Earlier papers have discussed the benefits of an integrated analysis environment for system-level thermal, stress and EMC prediction. This paper focuses on developments made to the stress analysis module and presents results obtained for an SMT resistor. Lifetime predictions are made using the Coffin-Manson equation. Comparison with the creep strain energy based models of Darveaux (1997) shows the shear strain based method to underestimate the solder joint life. Conclusions are also made about the capabilities of both approaches to predict the qualitative and quantitative impact of design changes.
Resumo:
Flip-chip assembly, developed in the early 1960s, is now being positioned as a key joining technology to achieve high-density mounting of electronic components on to printed circuit boards for high-volume, low-cost products. Computer models are now being used early within the product design stage to ensure that optimal process conditions are used. These models capture the governing physics taking place during the assembly process and they can also predict relevant defects that may occur. Describes the application of computational modelling techniques that have the ability to predict a range of interacting physical phenomena associated with the manufacturing process. For example, in the flip-chip assembly process we have solder paste deposition, solder joint shape formation, heat transfer, solidification and thermal stress. Illustrates the application of modelling technology being used as part of a larger UK study aiming to establish a process route for high-volume, low-cost, sub-100-micron pitch flip-chip assembly.
Resumo:
In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal–mechanical fatigue life of flip chips with no-flow underfill.
Resumo:
Four non-destructive tests for determining the length of fatigue cracks within the solder joints of a 2512 surface mount resistor are investigated. The sensitivity of the tests is obtained using finite element analysis with some experimental validation. Three of the tests are mechanically based and one is thermally based. The mechanical tests all operate by applying different loads to the PCB and monitoring the strain response at the top of the resistor. The thermal test operates by applying a heat source underneath the PCB, and monitoring the temperature response at the top of the resistor. From the modelling work done, two of these tests have shown to be sensitive to cracks. Some experimental results are presented but further work is required to fully validate the simulation results.
Resumo:
In this paper, the effects of the solder reflow process on the reliability of anisotropic conductive film (ACF) interconnections for flip chip on flex (FCOF) applications are investigated. Experiments as well as computer modeling methods have been used. In the experiments, it was found that the contact resistance of ACF joints increased after the subsequent reflow process, and the magnitude of this increase was strongly correlated to the peak temperature of the reflow profile. Nearly 40% of the joints were opened (i.e. lifted away from the pad) after the reflow process with 260 °C peak temperature while no opening was observed when the peak temperature was 210 °C. It is believed that the CTE mismatch between the polymer particle and the adhesive matrix is the main cause of this contact degradation. It was also found that the ACF joints after the reflow process with 210 °C peak temperature showed a high ability to resist water absorption under steady state 85 °C/85%RH conditions, probably because the curing degree of the ACF was improved during the reflow process. To give a good understanding, a 3D model of an ACF joint structure was built and finite element analysis was used to predict the stress distribution in the conductive particles, adhesive matrix and metal pads during the reflow process.
Resumo:
Recently, research has been carried out to test a novel bumping method which omits the under bump metallurgy (UBM) forming process by bonding copper columns directly onto the Al pads of the silicon dies. This bumping method could be adopted to simplify the flip chip assembly process, increase the productivity and achieve a higher I/O count. Computer modelling methods are used to predict the shape of solder joints and response of the flip chip to thermal cyclic loading. The accumulated plastic strain energy at the comer solder joints is used as the damage indicator. Models with a range of design parameters have been compared for their reliability. The ranking of the relative importance of these parameters is given. Results from these analyses are being used by our industrial and academic partners to identify optimal design conditions.
Resumo:
For sensitive optoelectronic components, traditional soldering techniques cannot be used because of their inherent sensitivity to thermal stresses. One such component is the Optoelectronic Butterfly Package which houses a laser diode chip aligned to a fibre-optic cable. Even sub-micron misalignment of the fibre optic and laser diode chip can significantly reduce the performance of the device. The high cost of each unit requires that the number of damaged components, via the laser soldering process, are kept to a minimum. Mathematical modelling is undertaken to better understand the laser soldering process and to optimize operational parameters such as solder paste volume, copper pad dimensions, laser solder times for each joint, laser intensity and absorption coefficient. Validation of the model against experimental data will be completed, and will lead to an optimization of the assembly process, through an iterative modelling cycle. This will ultimately reduce costs, improve the process development time and increase consistency in the laser soldering process.
Resumo:
Recently, research has been carried out to test a novel bumping method which omits the under bump metallurgy forming process by bonding copper columns directly onto the Al pads of the silicon dies. This bumping method could be adopted to simplify the flip chip manufacturing process, increase the productivity and achieve a higher I/O count. This paper describes an investigation of the solder joint reliability of flip-chips based on this new bumping process. Computer modelling methods are used to predict the shape of solder joints and response of flip chips to thermal cyclic loading. The accumulated plastic strain energy at the comer solder joints is used as the damage indicator. Models with a range of design parameters have been compared for their reliability. The parameters that have been investigated are the copper column height, radius and solder volume. The ranking of the relative importance of these parameters is given. For most of the results presented in the paper, the solder material has been assumed to be the lead-free 96.5Sn3.5Ag alloy but some results for 60Sn40Pb solder joints have also been presented.
Resumo:
The aim of integrating computational mechanics (FEA and CFD) and optimization tools is to speed up dramatically the design process in different application areas concerning reliability in electronic packaging. Design engineers in the electronics manufacturing sector may use these tools to predict key design parameters and configurations (i.e. material properties, product dimensions, design at PCB level. etc) that will guarantee the required product performance. In this paper a modeling strategy coupling computational mechanics techniques with numerical optimization is presented and demonstrated with two problems. The integrated modeling framework is obtained by coupling the multi-physics analysis tool PHYSICA - with the numerical optimization package - Visua/DOC into a fuJly automated design tool for applications in electronic packaging. Thermo-mechanical simulations of solder creep deformations are presented to predict flip-chip reliability and life-time under thermal cycling. Also a thermal management design based on multi-physics analysis with coupled thermal-flow-stress modeling is discussed. The Response Surface Modeling Approach in conjunction with Design of Experiments statistical tools is demonstrated and used subsequently by the numerical optimization techniques as a part of this modeling framework. Predictions for reliable electronic assemblies are achieved in an efficient and systematic manner.
Resumo:
Cu column bumping is a novel flip chip packaging technique that allows Cu columns to be bonded directly with the dies. It has eliminated the under-bump-metallurgy (UBM) fonnation step of the traditional flip chip manufacturing process. This bumping technique has the potential benefits of simplifying the flip chip manufacturing process, increasing productivity and the UO counts. In this paper, a study of reliability of Cu column bumped flip chips will be presented. Computer modelling methods have been used to predict the shape of solder joints and the response of flip chips to cyclic thermal-mechanical loading. The accumulated plastic strain energy at the corner solder joints has been used as an indicator of the solder joint reliability. Models with a wide range of design parameters have been compared for their reliability. The design parameters that have been investigated are the copper column height and radius, PCB pad radius, solder volume and Cu column wetting height. The relative importance ranking of these parameters has been obtained. The Lead-free solder material 96.5Sn3.5Ag has been used in this modelling work.
Resumo:
In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfills as the application and curing of this type of underfill can be undertaken before and during the reflow process - adding high volume throughput. Adopting a no-flow underfill process may result in underfill entrapment between solder and fluid, voiding in the underfill, a possible delamination between underfill and surrounding surfaces. The magnitude of these phenomena may adversely affect the reliability of the assembly in terms of solder joint thermal fatigue. This paper presents both an experimental and mdeling analysis investigating the reliabity of a flip-chip component and how the magnitude of underfill entrapment may affect thermal-mechanical fatigue life.
Resumo:
This article presents the latest print results at less than 100 microns pitch obtained in stencil printing type 6 and 7 lead-free solder pastes and conductive adhesives. The advantages of the microengineered stencil arc presented and compared with other bonding technologies. Characterisation of the print deposits is presented and future applications of stencil printing are described.
Resumo:
Compuational fluid dynamics (CFD) is used to help understand the gas flow characteristics in the wave soldering process. CFD has the ability to calculate (1) heal transfer, (2) fluid dynamics, and (3) oxygen concentration throughout the wave soldering machine. Understanding the impact of fluid dynamics on oxygen concentration is important as excessive oxygen at the solder bath can lead to high dross contents and hence poor solder joint quality on the printed circuit board. This paper describes the CFD modelling approach and illustrates its capability for a machine which has nitrogen injectors near the solder bath. Different magnitiutes of nitrogen flow rates are investigated and it is demonstrated how these effect the oxygen concentration at the bath surface.