Modelling the Lamination Process for Ruggedised Displays

Active matrix liquid crystal displays (AMLCD) need to be protected in severe environments. This is achieved through a ruggedisation process, where the display is laminated with cover glasses to become a more robust structure. The ruggedisation process can in itself cause stresses in the display and this can lead to delamination failures during the lamination process, during qualification testing or in-service. Controlling the magnitude of stress in a display during the lamination process is of course very important and this depends highly on the materials used. This paper discusses the use of finite element analysis to investigate the use of different materials in the lamination process and how such materials can affect the stress magnitude in the display.

Thermo-mechanical modelling of power electronics module structures

Power electronic modules distinguish themselves from other modules by their high power operation. These modules are used extensively in high power application markets such as aerospace, automotive, industrial and traction and drives. This paper discusses typical packaging technologies for power electronics modules. It also discusses the latest results from a UK research project investigating the physics-of-failure approach to reliability analysis and predictions for power modules. An integrated design enviroment for incorporating of affects of uncertainty into the design environment was outlined.

Predicting the behaviour of micro-electronic displays using computational mechanics

Micro-electronic displays are indispensible devices used in high performance applications such as aerospace, medical, marine and industrial sectors.These devices provide an interface to real time mission critical devices and therefore require good optical visual performance and high reliability, all this within varied and challenging environments.

Assessment of microInductors for DC-DC converters

There are increasing demands on the power density and efficiency of DC-DC power converters due to the soaring functionality and operational longevity required for today's electronic products. In addition, DC-DC converters are required to operate at new elevated frequencies in the MHz frequency regime. Typical ferrite cores, whose useable flux density falls drastically at these frequencies, have to be replaced and a method of producing compact component windings developed. In this study, two types of microinductors, pot-core and solenoid, for DC-DC converter applications have been analyzed for their performance in the MHz frequency range. The inductors were manufactured using an adapted UV-LIGA process and included electrodeposited nickel-iron and the commercial alloy Vitrovac 6025 as core materials. Using a vibrating sample magnetometer (VSM) and a Hewlett Packard 4192A LF- impedance analyzer, the inductor characteristics such as power density, efficiency, inductance and Q-factor were recorded. Experimental, finite element and analytical results were used to assess the suitability of the magnetic materials and component geometries for low MHz operation.

Review of the technology and reliability issues arising as optical interconnects migrate onto the circuit board

Light has the greatest information carrying potential of all the perceivable interconnect mediums; consequently, optical fiber interconnects rapidly replaced copper in telecommunications networks, providing bandwidth capacity far in excess of its predecessors. As a result the modern telecommunications infrastructure has evolved into a global mesh of optical networks with VCSEL’s (Vertical Cavity Surface Emitting Lasers) dominating the short-link markets, predominately due to their low-cost. This cost benefit of VCSELs has allowed optical interconnects to again replace bandwidth limited copper as bottlenecks appear on VSR (Very Short Reach) interconnects between co-located equipment inside the CO (Central-Office). Spurred by the successful deployment in the VSR domain and in response to both intra-board backplane applications and inter-board requirements to extend the bandwidth between IC’s (Integrated Circuits), current research is migrating optical links toward board level USR (Ultra Short Reach) interconnects. Whilst reconfigurable Free Space Optical Interconnect (FSOI) are an option, they are complicated by precise line-of-sight alignment conditions hence benefits exist in developing guided wave technologies, which have been classified into three generations. First and second generation technologies are based upon optical fibers and are both capable of providing a suitable platform for intra-board applications. However, to allow component assembly, an integral requirement for inter-board applications, 3rd generation Opto-Electrical Circuit Boards (OECB’s) containing embedded waveguides are desirable. Currently, the greatest challenge preventing the deployment of OECB’s is achieving the out-of-plane coupling to SMT devices. With the most suitable low-cost platform being to integrate the optics into the OECB manufacturing process, several research avenues are being explored although none to date have demonstrated sufficient coupling performance. Once in place, the OECB assemblies will generate new reliability issues such as assembly configurations, manufacturing tolerances, and hermetic requirements that will also require development before total off-chip photonic interconnection can truly be achieved

Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process

This paper presents the results of a packaging process based on the stencil printing of isotropic conductive adhesives (ICAs) that form the interconnections of flip-chip bonded electronic packages. Ultra-fine pitch (sub-100-mum), low temperature (100degC), and low cost flip-chip assembly is demonstrated. The article details recent advances in electroformed stencil manufacturing that use microengineering techniques to enable stencil fabrication at apertures sizes down to 20mum and pitches as small as 30mum. The current state of the art for stencil printing of ICAs and solder paste is limited between 150-mum and 200-mum pitch. The ICAs-based interconnects considered in this article have been stencil printed successfully down to 50-mum pitch with consistent printing demonstrated at 90-mum pitch size. The structural integrity or the stencil after framing and printing is also investigated through experimentation and computational modeling. The assembly of a flip-chip package based on copper column bumped die and ICA deposits stencil printed at sub-100-mum pitch is described. Computational fluid dynamics modeling of the print performance provides an indicator on the optimum print parameters. Finally, an organic light emitting diode display chip is packaged using this assembly process

Wire bond reliability for power electronic modules - effect of bonding temperature

In this paper, thermal cycling reliability along with ANSYS analysis of the residual stress generated in heavy-gauge Al bond wires at different bonding temperatures is reported. 99.999% pure Al wires of 375 mum in diameter, were ultrasonically bonded to silicon dies coated with a 5mum thick Al metallisation at 25degC (room temperature), 100degC and 200degC, respectively (with the same bonding parameters). The wire bonded samples were then subjected to thermal cycling in air from -60degC to +150degC. The degradation rate of the wire bonds was assessed by means of bond shear test and via microstructural characterisation. Prior to thermal cycling, the shear strength of all of the wire bonds was approximately equal to the shear strength of pure aluminum and independent of bonding temperature. During thermal cycling, however, the shear strength of room temperature bonded samples was observed to decrease more rapidly (as compared to bonds formed at 100degC and 200degC) as a result of a high crack propagation rate across the bonding area. In addition, modification of the grain structure at the bonding interface was also observed with bonding temperature, leading to changes in the mechanical properties of the wire. The heat and pressure induced by the high temperature bonding is believed to promote grain recovery and recrystallisation, softening the wires through removal of the dislocations and plastic strain energy. Coarse grains formed at the bonding interface after bonding at elevated temperatures may also contribute to greater resistance for crack propagation, thus lowering the wire bond degradation rate

Lifetime prediction for power electronics module substrate mount-down solder interconnect

A numerical modeling method for the prediction of the lifetime of solder joints of relatively large solder area under cyclic thermal-mechanical loading conditions has been developed. The method is based on the Miner's linear damage accumulation rule and the properties of the accumulated plastic strain in front of the crack in large area solder joint. The nonlinear distribution of the damage indicator in the solder joints have been taken into account. The method has been used to calculate the lifetime of the solder interconnect in a power module under mixed cyclic loading conditions found in railway traction control applications. The results show that the solder thickness is a parameter that has a strong influence on the damage and therefore the lifetime of the solder joint while the substrate width and the thickness of the baseplate are much less important for the lifetime

Reliability of power electronic modules

The electric car, the all electric aircraft and requirements for renewable energy are examples of potential technologies needed to address the world problem of global warming/carbon emission etc. Power electronics and packaged modules are fundamental for the underpinning of these technologies and with the diverse requirements for electrical configurations and the range of environmental conditions, time to market is paramount for module manufacturers and systems designers alike. This paper details some of the results from a major UK project into the reliability of power electronic modules using physics of failure techniques. This paper presents a design methodology together with results that demonstrate enhanced product design with improved reliability, performance and value within acceptable time scales

Open ended microwave oven for flip-chip assembly

A novel open-ended waveguide cavity resonator for the microwave curing of bumps, underfills and encapsulants is described. The open oven has the potential to provide fast alignment of devices during flip-chip assembly, direct chip attach, surface mount assembly or wafer-scale level packaging. The prototype microwave oven was designed to operate at X-band for ease of testing, although a higher frequency version is planned. The device described in the paper takes the form of a waveguide cavity resonator. It is approximately square in cross-section and is filled with a low-loss dielectric with a relative permittivity of 6. It is excited by end-fed probes in order to couple power preferentially into the TM3,3,k mode with the object of forming nine 'hot-spots' in the open end. Low power tests using heat sensitive film demonstrate clearly that selective heating in multiple locations in the open end of the oven is achievable

Shear strength analysis of ball grid array (BGA) solder interfaces

Ball shear test is the most common test method used to assess the reliability of bond strength for ball grid array (BGA) packages. In this work, a combined experimental and numerical study was carried out to realize of BGA solder interface strength. Solder mask defined bond pads on the BGA substrate were used for BGA ball bonding. Different bond pad metallizations and solder alloys were used. Solid state aging at 150degC up to 1000 h has been carried out to change the interfacial microstructure. Cross-sectional studies of the solder-to-bond pad interfaces was conducted by scanning electron microscopy (SEM) equipped with an energy dispersive X-ray (EDX) analyzer to investigate the interfacial reaction phenomena. Ball shear tests have been carried out to obtain the mechanical strength of the solder joints and to correlate shear behaviour with the interfacial reaction products. An attempt has been taken to realize experimental findings by Finite Element Analysis (FEA). It was found that intermetallic compound (IMC) formation at the solder interface plays an important role in the BGA solder bond strength. By changing the morphology and the microchemistry of IMCs, the fracture propagation path could be changed and hence, reliability could be improved

A modelling approach for coupling numerical analytical techniques applied in microsystems

In this paper, a method for the integration of several numerical analytical techniques that are used in microsystems design and failure analysis is presented. The analytical techniques are categorized into four groups in the discussion, namely the high-fidelity analytical tools, i.e. finite element (FE) method, the fast analytical tools referring to reduced order modeling (ROM); the optimization tools, and probability based analytical tools. The characteristics of these four tools are investigated. The interactions between the four tools are discussed and a methodology for the coupling of these four tools is offered. This methodology consists of three stages, namely reduced order modeling, deterministic optimization and probabilistic optimization. Using this methodology, a case study for optimization of a solder joint is conducted. It is shown that these analysis techniques have mutual relationship of interaction and complementation. Synthetic application of these techniques can fully utilize the advantages of these techniques and satisfy various design requirements. The case study shows that the coupling method of different tools provided by this paper is effective and efficient and it is highly relevant in the design and reliability analysis of microsystems

Performance and reliability of flexible substrates when subjected to lead-free processing

The use of flexible substrates is growing in many applications such as computer peripherals, hand held devices, telecommunications, automotive, aerospace, etc. The drive to adopt flexible circuits is due to their ability to reduce size, weight, assembly time and cost of the final product.They also accommodate flexibility by allowing relative movement between component parts and provide a route for three dimensional packaging. This paper will describe some of the current research results from the Flex-No-Lead project, a European Commission sponsored research program. The principle aim of this project is to investigate the processing, performance, and reliability of flexible substrates when subjected to new environmentally friendly, lead-free soldering technologies. This paper will discuss the impact of specific design variables on performance and reliability. In particular the paper will focus on copper track designs, substrate material, dielectric material and solder-mask defined joints.

Modelling the reliability of components on flexible substrates

The use of flexible substrates is growing in many applications such as computer peripherals, hand held devices, telecommunications, automotive, aerospace, etc. The drive to adopt flexible circuits is due to their ability to reduce size, weight, assembly time and cost of final product. they also accommodate flexibility by allowing relative movement between component parts and provide a route for three dimensional packaging. This paper will describe some of the current research results from the Flex-No-Lead project, European Commission sponsored programme. The principle aim of this project is to investigate the processing, performance and reliability of flexible substrates when subjected to new environmentally friendly, lead-free soldering technologies. This paper will discuss the impact of specific design variables on performance and reliability. In particular the paper will focus on copper track designs, substrate material, dielectric material and solder mask defined joints

Thermal analysis of LEDS for liquid crystal display's backlighting

This paper investigated the thermal design of the light emitting diode (LED)onto the board and its packaging. The LED was a 6-lead MultiLED with three chips designed for LCD backlighting and other lighting purposes. A 3D finite element model of this LED was built up and thermal analysis was carried out using the multi physics software package PHYSICA. The modeling results were presented as temperature distributions in each LED, and the predicted junction temperature was used for thermal resistance calculation. The results for the board structure indicated that (1) removing the foil attach decreased the thermal resistance, (2) Increasing the copper foil thickness reduced the thermal resistance. package design indicated that the SMT designed LED with integrated slug gave lower thermal resistance. Pb-free solder material gave lower thermal resistance and junction temperature when compared with conductive adhesive