Reliability analysis of flip chip designs via computer simulation

A flip chip component is a silicon chip mounted to a substrate with the active area facing the substrate. This paper presents the results of an investigation into the relationship between a number of important material properties and geometric parameters on the thermal-mechanical fatigue reliability of a standard flip chip design and a flip chip design with the use of microvias. Computer modeling has been used to analyze the mechanical conditions of flip chips under cyclic thermal loading where the Coffin-Manson empirical relationship has been used to predict the life time of the solder interconnects. The material properties and geometry parameters that have been investigated are the Young's modulus, the coefficient of thermal expansion (CTE) of the underfill, the out-of-plane CTE (CTEz) of the substrate, the thickness of the substrate, and the standoff height. When these parameters vary, the predicted life-times are calculated and some of the features of the results are explained. By comparing the predicted lifetimes of the two designs and the strain conditions under thermal loading, the local CTE mismatch has been found to be one of most important factors in defining the reliability of flip chips with microvias.

Modelling technology to predict flip-chip assembly

This paper describes modelling technology and its use in providing data governing the assembly of flip-chip components. Details are given on the reflow and curing stages as well as the prediction of solder joint shapes. The reflow process involves the attachment of a die to a board via solder joints. After a reflow process, underfill material is placed between the die and the substrate where it is heated and cured. Upon cooling the thermal mismatch between the die, underfill, solder bumps, and substrate will result in a nonuniform deformation profile across the assembly and hence stress. Shape predictions then thermal solidification and stress prediction are undertaken on solder joints during the reflow process. Both thermal and stress calculations are undertaken to predict phenomena occurring during the curing of the underfill material. These stresses may result in delamination between the underfill and its surrounding materials leading to a subsequent reduction in component performance and lifetime. Comparisons between simulations and experiments for die curvature will be given for the reflow and curing process

Modelling the effect of temperature on product reliability

Reliability of electronic parts is a major concern for many manufacturers, since early failures in the field can cost an enormous amount to repair - in many cases far more than the original cost of the product. A great deal of effort is expended by manufacturers to determine the failure rates for a process or the fraction of parts that will fail in a period of time. It is widely recognized that the traditional approach to reliability predictions for electronic systems are not suitable for today's products. This approach, based on statistical methods only, does not address the physics governing the failure mechanisms in electronic systems. This paper discusses virtual prototyping technologies which can predict the physics taking place and relate this to appropriate failure mechanisms. Simulation results illustrate the effect of temperature on the assembly process of an electronic package and the lifetime of a flip-chip package.

Modelling the performance of lead-Free solder interconnects for copper bumped flip-chip devices

Traditionally, before flip chips can be assembled the dies have to be attached with solder bumps. This process involves the deposition of metal layers on the Al pads on the dies and this is called the under bump metallurgy (UBM). In an alternative process, however, Copper (Cu) columns can be used to replace solder bumps and the UBM process may be omitted altogether. After the bumping process, the bumped dies can be assembled on to the printed circuit board (PCB) by using either solder or conductive adhesives. In this work, the reliability issues of flip chips with Cu column bumped dies have been studied. The flip chip lifetime associated with the solder fatigue failure has been modeled for a range of geometric parameters. The relative importance of these parameters is given and solder volume has been identified as the most important design parameter for long-term reliability. Another important problem that has been studied in this work is the dissolution of protection metals on the pad and Cu column in the reflow process. For small solder joints the amount of Cu which dissolves into the molten solder after the protection layers have worn out may significantly affect solder joint properties.

Computational modeling techniques for reliability of electronic components on printed circuit boards

This paper describes modeling technology and its use in providing data governing the assembly and subsequent reliability of electronic chip components on printed circuit boards (PCBs). Products, such as mobile phones, camcorders, intelligent displays, etc., are changing at a tremendous rate where newer technologies are being applied to satisfy the demands for smaller products with increased functionality. At ever decreasing dimensions, and increasing number of input/output connections, the design of these components, in terms of dimensions and materials used, is playing a key role in determining the reliability of the final assembly. Multiphysics modeling techniques are being adopted to predict a range of interacting physics-based phenomena associated with the manufacturing process. For example, heat transfer, solidification, marangoni fluid flow, void movement, and thermal-stress. The modeling techniques used are based on finite volume methods that are conservative and take advantage of being able to represent the physical domain using an unstructured mesh. These techniques are also used to provide data on thermal induced fatigue which is then mapped into product lifetime predictions.

Using computer models to identify optimal conditions for flip-chip assembly and reliability

Flip-chip assembly, developed in the early 1960s, is now being positioned as a key joining technology to achieve high-density mounting of electronic components on to printed circuit boards for high-volume, low-cost products. Computer models are now being used early within the product design stage to ensure that optimal process conditions are used. These models capture the governing physics taking place during the assembly process and they can also predict relevant defects that may occur. Describes the application of computational modelling techniques that have the ability to predict a range of interacting physical phenomena associated with the manufacturing process. For example, in the flip-chip assembly process we have solder paste deposition, solder joint shape formation, heat transfer, solidification and thermal stress. Illustrates the application of modelling technology being used as part of a larger UK study aiming to establish a process route for high-volume, low-cost, sub-100-micron pitch flip-chip assembly.

No-flow underfill flip chip assembly–an experimental and modeling analysis

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal–mechanical fatigue life of flip chips with no-flow underfill.

Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives

This paper discusses results from a highly interdisciplinary research project which investigated different packaging options for ultra-fine pitch, low temperature and low cost flip-chip assembly. Isotropic Conductive Adhesives (ICAs) are stencil printed to form the interconnects for the package. ICAs are utilized to ensure a low temperature assembly process of flip-chip copper column bumped packages. Results are presented on the structural integrity of novel electroformed stencils. ICA deposits at sub-100 micron pitch and the subsequent thermo-mechanical behaviour of the flip-chip ICA joints are analysed using numerical modelling techniques. Optimal design rules for enhanced performance and thermomechanical reliability of ICA assembled flip-chip packages are formulated.

Microwave cure of conductive adhesives for flip-chip & microsystems applications

The curing of conductive adhesives and underfills can save considerable time and offer cost benefits for the microsystems and electronics packaging industry. In contrast to conventional ovens, curing by microwave energy generates heat internally within each individual component of an assembly. The rate at which heat is generated is different for each of the components and depends on the material properties as well as the oven power and frequency. This leads to a very complex and transient thermal state, which is extremely difficult to measure experimentally. Conductive adhesives need to be raised to a minimum temperature to initiate the cross-linking of the resin polymers, whilst some advanced packaging materials currently under investigation impose a maximum temperature constraint to avoid damage. Thermal imagery equipment integrated with the microwave oven can offer some information on the thermal state but such data is based on the surface temperatures. This paper describes computational models that can simulate the internal temperatures within each component of an assembly including the critical region between the chip and substrate. The results obtained demonstrate that due to the small mass of adhesive used in the joints, the temperatures reached are highly dependent on the material properties of the adjacent chip and substrate.

A modelling and experimental analysis of the no-flow underfill process for flip-chip assembly

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfills as the application and curing of this type of underfill can be undertaken before and during the reflow process - adding high volume throughput. Adopting a no-flow underfill process may result in underfill entrapment between solder and fluid, voiding in the underfill, a possible delamination between underfill and surrounding surfaces. The magnitude of these phenomena may adversely affect the reliability of the assembly in terms of solder joint thermal fatigue. This paper presents both an experimental and mdeling analysis investigating the reliabity of a flip-chip component and how the magnitude of underfill entrapment may affect thermal-mechanical fatigue life.

Dynamic analysis of Flip-Chip Self-Alignment

Self-alignment of soldered electronic components such as flip-chips (FC), ball grid arrays (BGA) and optoelectronic devices during solder reflow is important as it ensures good alignment between components and substrates. Two uncoupled analytical models are presented which provide estimates of the dynamic time scales of both the chip and the solder in the self-alignment process. These predicted time scales can be used to decide whether a coupled dynamic analysis is required for the analysis of the chip motion. In this paper, we will show that for flip-chips, the alignment dynamics can be described accurately only when the chip motion is coupled with the solder motion because the two have similar time-scale values. To study this coupled phenomenon, a dynamic modeling method has been developed. The modeling results show that the uncoupled and coupled calculations result in significantly different predictions. The calculations based on the coupled model predict much faster rates of alignment than those predicted using the uncoupled approach.

Moisture Effects on the Reliability of Anisotropic Conductive Films

Anisotropic conductive film (ACF) which consists of an adhesive epoxy matrix and randomly distributed conductive particles are widely used as the connection material for electronic devices with high I/O counts. However, for the semiconductor industry the reliability of the ACF is still a major concern due to a lack of experimental reliability data. This paper reports an investigation into the moisture effects on the reliability of ACF interconnections in the flip-chip-on-flex (FCOF) applications. A macro-micro 3D finite element modeling technique was used in order to make the multi-length-scale modeling of the ACF flip chip possible. The purposes of this modeling work was to understand the role that moisture plays in the failure of ACF flip chips, and to look into the influence of physical properties and geometric characteristics, such as the coefficient of the moisture expansion (CME), Young's modulus of the adhesive matrix and the bump height on the reliability of the ACF interconnections in a humid environment. Simulation results suggest that moisture-induced swelling of the adhesive matrix is the major cause of the ACF joint opening. Modeling results are consistent with the findings in the experimental work.

Computational modelling for reliable flip-chip packaging at sub-100 micron pitch using isotropic conductive adhesives

This paper presents the assembly process using next generation electroformed stencils and Isotropic Conductive Adhesives (ICAs) as interconnection material. The utilisation of ICAs in flip-chip assembly process is investigated as an alternative to the lead and lead-free solder alloys and aims to ensure a low temperature (T < 100 °C) assembly process. The paper emphasizes and discusses in details the assembly of a flip-chip package based on copper columns bumped die and substrate with stencil printed ICA deposits at sub-100 μm pitch. A computational modelling approach is undertaken to provide comprehensive results on reliability trends of ICA joints subject to thermal cycling of the flip-chip assembly based on easy to use damage criteria and damage evaluation. Important design parameters in the package are selected and investigated using numerical modelling techniques to provide knowledge and understanding of their impact on the thermo-mechanical behaviour of the flip-chip ICA joints. Sensitivity analysis of the damage in the adhesive material is also carried out. Optimal design rules for enhanced performance and improved thermo-mechanical reliability of ICA assembled flip-chip packages are finally formulated.

Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process

This paper presents the results of a packaging process based on the stencil printing of isotropic conductive adhesives (ICAs) that form the interconnections of flip-chip bonded electronic packages. Ultra-fine pitch (sub-100-mum), low temperature (100degC), and low cost flip-chip assembly is demonstrated. The article details recent advances in electroformed stencil manufacturing that use microengineering techniques to enable stencil fabrication at apertures sizes down to 20mum and pitches as small as 30mum. The current state of the art for stencil printing of ICAs and solder paste is limited between 150-mum and 200-mum pitch. The ICAs-based interconnects considered in this article have been stencil printed successfully down to 50-mum pitch with consistent printing demonstrated at 90-mum pitch size. The structural integrity or the stencil after framing and printing is also investigated through experimentation and computational modeling. The assembly of a flip-chip package based on copper column bumped die and ICA deposits stencil printed at sub-100-mum pitch is described. Computational fluid dynamics modeling of the print performance provides an indicator on the optimum print parameters. Finally, an organic light emitting diode display chip is packaged using this assembly process

On the application of variable frequency microwave technology for processing of individual surface mount components

Dual-section variable frequency microwave systems enable rapid, controllable heating of materials within an individual surface mount component in a chip-on=board assembly. The ability to process devices individually allows components with disparate processing requirements to be mounted on the same assembly. The temperature profile induced by the microwave system can be specifically tailored to the needs of the component, allowing optimisation and degree of cure whilst minimising thermomechanical stresses. This paper presents a review of dual-section microwave technology and its application to curing of thermosetting polymer materials in microelectronics applications. Curing processes using both conventional and microwave technologies are assessed and compared. Results indicate that dual-section microwave systems are able to cure individual surface mount packages in a significantly shorter time, at the expense of an increase in thermomechanical stresses and a greater variation in degree of cure.