Testing of Interposer-Based 2.5D Integrated Circuits

The unprecedented and relentless growth in the electronics industry is feeding the demand for integrated circuits (ICs) with increasing functionality and performance at minimum cost and power consumption. As predicted by Moore's law, ICs are being aggressively scaled to meet this demand. While the continuous scaling of process technology is reducing gate delays, the performance of ICs is being increasingly dominated by interconnect delays. In an effort to improve submicrometer interconnect performance, to increase packing density, and to reduce chip area and power consumption, the semiconductor industry is focusing on three-dimensional (3D) integration. However, volume production and commercial exploitation of 3D integration are not feasible yet due to significant technical hurdles.

At the present time, interposer-based 2.5D integration is emerging as a precursor to stacked 3D integration. All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. However, since the structure of 2.5D ICs is different from the traditional 2D ICs, new challenges have emerged: (1) pre-bond interposer testing, (2) lack of test access, (3) limited ability for at-speed testing, (4) high density I/O ports and interconnects, (5) reduced number of test pins, and (6) high power consumption. This research targets the above challenges and effective solutions have been developed to test both dies and the interposer.

The dissertation first introduces the basic concepts of 3D ICs and 2.5D ICs. Prior work on testing of 2.5D ICs is studied. An efficient method is presented to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of a die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing.

In order to test for opens, shorts, and interconnect delay defects in the interposer, a test architecture is proposed that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. To reduce test cost, a test-path design and scheduling technique is also presented that minimizes a composite cost function based on test time and the design-for-test (DfT) overhead in terms of additional through silicon vias (TSVs) and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a test path.

To address the scenario of high density of I/O ports and interconnects, an efficient built-in self-test (BIST) technique is presented that targets the dies and the interposer interconnects. The proposed BIST architecture can be enabled by the standard TAP controller in the IEEE 1149.1 standard. The area overhead introduced by this BIST architecture is negligible; it includes two simple BIST controllers, a linear-feedback-shift-register (LFSR), a multiple-input-signature-register (MISR), and some extensions to the boundary-scan cells in the dies on the interposer. With these extensions, all boundary-scan cells can be used for self-configuration and self-diagnosis during interconnect testing. To reduce the overall test cost, a test scheduling and optimization technique under power constraints is described.

In order to accomplish testing with a small number test pins, the dissertation presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an system on chip (SoC) die on the interposer while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group.

Finally, the dissertation presents a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. An SoC die in the 2.5D IC is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated.

In summary, the dissertation targets important design and optimization problems related to testing of interposer-based 2.5D ICs. The proposed research has led to theoretical insights, experiment results, and a set of test and design-for-test methods to make testing effective and feasible from a cost perspective.

Small-scale Fisheries and the Global Economy: Understanding Common-pool Resource Governance in the Context of Market Pressures, Neoliberal Policies, and Transnational Institutions

The purpose of this dissertation is to contribute to a better understanding of how global seafood trade interacts with the governance of small-scale fisheries (SSFs). As global seafood trade expands, SSFs have the potential to experience significant economic, social, and political benefits from participation in export markets. At the same time, market connections that place increasing pressures on resources pose risks to both the ecological and social integrity of SSFs. This dissertation seeks to explore the factors that mediate between the potential benefits and risks of global seafood markets for SSFs, with the goal of developing hypotheses regarding these relationships.

The empirical investigation consists of a series of case studies from the Yucatan Peninsula, Mexico. This is a particularly rich context in which to study global market connections with SSFs because the SSFs in this region engage in a variety of market-oriented harvests, most notably for octopus, groupers and snappers, lobster, and sea cucumber. Variation in market forms and the institutional diversity of local-level governance arrangements allows the dissertation to explore a number of examples.

The analysis is guided primarily by common-pool resource (CPR) theory because of the insights it provides regarding the conditions that facilitate collective action and the factors that promote long-lasting resource governance arrangements. Theory from institutional economics and political ecology contribute to the elaboration of a multi-faceted conceptualization of markets for CPR theory, with the aim of facilitating the identification of mechanisms through which markets and CPR governance actually interact. This dissertation conceptualizes markets as sets of institutions that structure the exchange of property rights over fisheries resources, affect the material incentives to harvest resources, and transmit ideas and values about fisheries resources and governance.

The case studies explore four different mechanisms through which markets potentially influence resource governance: 1) Markets can contribute to costly resource governance activities by offsetting costs through profits, 2) markets can undermine resource governance by generating incentives for noncompliance and lead to overharvesting resources, 3) markets can increase the costs of resource governance, for example by augmenting monitoring and enforcement burdens, and 4) markets can alter values and norms underpinning resource governance by transmitting ideas between local resource users and a variety of market actors.

Data collected using participant observation, survey, informal and structured interviews contributed to the elaboration of the following hypotheses relevant to interactions between global seafood trade and SSFs governance. 1) Roll-back neoliberalization of fisheries policies has undermined cooperatives’ ability to achieve financial success through engagement with markets and thus their potential role as key actors in resource governance (chapter two). 2) Different relations of production influence whether local governance institutions will erode or strengthen when faced with market pressures. In particular, relations of production in which fishers own their own means of production and share the collective costs of governance are more likely to strengthen resource governance while relations of production in which a single entrepreneur controls capital and access to the fishery are more likely to contribute to the erosion of resource governance institutions in the face of market pressures (chapter three). 3) By serving as a new discursive framework within which to conceive of and talk about fisheries resources, markets can influence norms and values that shape and constitute governance arrangements.

In sum, the dissertation demonstrates that global seafood trade manifests in a diversity of local forms and effects. Whether SSFs moderate risks and take advantage of benefits depends on a variety of factors, and resource users themselves have the potential to influence the outcomes of seafood market connections through local forms of collective action.