Improving Indwelling Glucose Sensor Performance: Porous, Dexamethasone-Releasing Coatings that Modulate the Foreign Body Response

Inflammation and the formation of an avascular fibrous capsule have been identified as the key factors controlling the wound healing associated failure of implantable glucose sensors. Our aim is to guide advantageous tissue remodeling around implanted sensor leads by the temporal release of dexamethasone (Dex), a potent anti-inflammatory agent, in combination with the presentation of a stable textured surface.

First, Dex-releasing polyurethane porous coatings of controlled pore size and thickness were fabricated using salt-leaching/gas-foaming technique. Porosity, pore size, thickness, drug release kinetics, drug loading amount, and drug bioactivity were evaluated. In vitro sensor functionality test were performed to determine if Dex-releasing porous coatings interfered with sensor performance (increased signal attenuation and/or response times) compared to bare sensors. Drug release from coatings monitored over two weeks presented an initial fast release followed by a slower release. Total release from coatings was highly dependent on initial drug loading amount. Functional in vitro testing of glucose sensors deployed with porous coatings against glucose standards demonstrated that highly porous coatings minimally affected signal strength and response rate. Bioactivity of the released drug was determined by monitoring Dex-mediated, dose-dependent apoptosis of human peripheral blood derived monocytes in culture.

The tissue modifying effects of Dex-releasing porous coatings were accessed by fully implanting Tygon® tubing in the subcutaneous space of healthy and diabetic rats. Based on encouraging results from these studies, we deployed Dex-releasing porous coatings from the tips of functional sensors in both diabetic and healthy rats. We evaluated if the tissue modifying effects translated into accurate, maintainable and reliable sensor signals in the long-term. Sensor functionality was accessed by continuously monitoring glucose levels and performing acute glucose challenges at specified time points.

Sensors treated with porous Dex-releasing coatings showed diminished inflammation and enhanced vascularization of the tissue surrounding the implants in healthy rats. Functional sensors with Dex-releasing porous coatings showed enhanced sensor sensitivity over a 21-day period when compared to controls. Enhanced sensor sensitivity was accompanied with an increase in sensor signal lag and MARD score. These results indicated that Dex-loaded porous coatings were able to elicit a favorable tissue response, and that such tissue microenvironment could be conducive towards extending the performance window of glucose sensors in vivo.

The diabetic pilot animal study showed differences in wound healing patters between healthy and diabetic subjects. Diabetic rats showed lower levels of inflammation and vascularization of the tissue surrounding implants when compared to their healthy counterparts. Also, functional sensors treated with Dex-releasing porous coatings did not show enhanced sensor sensitivity over a 21-day period. Moreover, increased in sensor signal lag and MARD scores were present in porous coated sensors regardless of Dex-loading when compared to bare implants. These results suggest that the altered wound healing patterns presented in diabetic tissues may lead to premature sensor failure when compared to sensors implanted in healthy rats.

Testing of Interposer-Based 2.5D Integrated Circuits

The unprecedented and relentless growth in the electronics industry is feeding the demand for integrated circuits (ICs) with increasing functionality and performance at minimum cost and power consumption. As predicted by Moore's law, ICs are being aggressively scaled to meet this demand. While the continuous scaling of process technology is reducing gate delays, the performance of ICs is being increasingly dominated by interconnect delays. In an effort to improve submicrometer interconnect performance, to increase packing density, and to reduce chip area and power consumption, the semiconductor industry is focusing on three-dimensional (3D) integration. However, volume production and commercial exploitation of 3D integration are not feasible yet due to significant technical hurdles.

At the present time, interposer-based 2.5D integration is emerging as a precursor to stacked 3D integration. All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. However, since the structure of 2.5D ICs is different from the traditional 2D ICs, new challenges have emerged: (1) pre-bond interposer testing, (2) lack of test access, (3) limited ability for at-speed testing, (4) high density I/O ports and interconnects, (5) reduced number of test pins, and (6) high power consumption. This research targets the above challenges and effective solutions have been developed to test both dies and the interposer.

The dissertation first introduces the basic concepts of 3D ICs and 2.5D ICs. Prior work on testing of 2.5D ICs is studied. An efficient method is presented to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of a die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing.

In order to test for opens, shorts, and interconnect delay defects in the interposer, a test architecture is proposed that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. To reduce test cost, a test-path design and scheduling technique is also presented that minimizes a composite cost function based on test time and the design-for-test (DfT) overhead in terms of additional through silicon vias (TSVs) and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a test path.

To address the scenario of high density of I/O ports and interconnects, an efficient built-in self-test (BIST) technique is presented that targets the dies and the interposer interconnects. The proposed BIST architecture can be enabled by the standard TAP controller in the IEEE 1149.1 standard. The area overhead introduced by this BIST architecture is negligible; it includes two simple BIST controllers, a linear-feedback-shift-register (LFSR), a multiple-input-signature-register (MISR), and some extensions to the boundary-scan cells in the dies on the interposer. With these extensions, all boundary-scan cells can be used for self-configuration and self-diagnosis during interconnect testing. To reduce the overall test cost, a test scheduling and optimization technique under power constraints is described.

In order to accomplish testing with a small number test pins, the dissertation presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an system on chip (SoC) die on the interposer while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group.

Finally, the dissertation presents a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. An SoC die in the 2.5D IC is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated.

In summary, the dissertation targets important design and optimization problems related to testing of interposer-based 2.5D ICs. The proposed research has led to theoretical insights, experiment results, and a set of test and design-for-test methods to make testing effective and feasible from a cost perspective.