EXPLICIT WRITTEN CORRECTIVE FEEDBACK AND LANGUAGE APTITUDE IN SLA: IMPLICATIONS FOR IMPROVEMENT OF LINGUISTIC ACCURACY

Most second language researchers agree that there is a role for corrective feedback in second language writing classes. However, many unanswered questions remain concerning which linguistic features to target and the type and amount of feedback to offer. This study examined two new pieces of writing by 151 learners of English as a Second Language (ESL), in order to investigate the effect of direct and metalinguistic written feedback on errors with the simple past tense, the present perfect tense, dropped pronouns, and pronominal duplication. This inquiry also considered the extent to which learner differences in language-analytic ability (LAA), as measured by the LLAMA F, mediated the effects of these two types of explicit written corrective feedback. Learners in the feedback groups were provided with corrective feedback on two essays, after which learners in all three groups completed two additional writing tasks to determine whether or not the provision of corrective feedback led to greater gains in accuracy compared to no feedback. Both treatment groups, direct and metalinguistic, performed better than the comparison group on new pieces of writing immediately following the treatment sessions, yet direct feedback was more durable than metalinguistic feedback for one structure, the simple past tense. Participants with greater LAA proved more likely to achieve gains in the direct feedback group than in the metalinguistic group, whereas learners with lower LAA benefited more from metalinguistic feedback. Overall, the findings of the present study confirm the results of prior studies that have found a positive role for written corrective feedback in instructed second language acquisition.

Architectural-Physical Co-Design of 3D CPUs with Micro-Fluidic Cooling

The performance, energy efficiency and cost improvements due to traditional technology scaling have begun to slow down and present diminishing returns. Underlying reasons for this trend include fundamental physical limits of transistor scaling, the growing significance of quantum effects as transistors shrink, and a growing mismatch between transistors and interconnects regarding size, speed and power. Continued Moore's Law scaling will not come from technology scaling alone, and must involve improvements to design tools and development of new disruptive technologies such as 3D integration. 3D integration presents potential improvements to interconnect power and delay by translating the routing problem into a third dimension, and facilitates transistor density scaling independent of technology node. Furthermore, 3D IC technology opens up a new architectural design space of heterogeneously-integrated high-bandwidth CPUs. Vertical integration promises to provide the CPU architectures of the future by integrating high performance processors with on-chip high-bandwidth memory systems and highly connected network-on-chip structures. Such techniques can overcome the well-known CPU performance bottlenecks referred to as memory and communication wall. However the promising improvements to performance and energy efficiency offered by 3D CPUs does not come without cost, both in the financial investments to develop the technology, and the increased complexity of design. Two main limitations to 3D IC technology have been heat removal and TSV reliability. Transistor stacking creates increases in power density, current density and thermal resistance in air cooled packages. Furthermore the technology introduces vertical through silicon vias (TSVs) that create new points of failure in the chip and require development of new BEOL technologies. Although these issues can be controlled to some extent using thermal-reliability aware physical and architectural 3D design techniques, high performance embedded cooling schemes, such as micro-fluidic (MF) cooling, are fundamentally necessary to unlock the true potential of 3D ICs. A new paradigm is being put forth which integrates the computational, electrical, physical, thermal and reliability views of a system. The unification of these diverse aspects of integrated circuits is called Co-Design. Independent design and optimization of each aspect leads to sub-optimal designs due to a lack of understanding of cross-domain interactions and their impacts on the feasibility region of the architectural design space. Co-Design enables optimization across layers with a multi-domain view and thus unlocks new high-performance and energy efficient configurations. Although the co-design paradigm is becoming increasingly necessary in all fields of IC design, it is even more critical in 3D ICs where, as we show, the inter-layer coupling and higher degree of connectivity between components exacerbates the interdependence between architectural parameters, physical design parameters and the multitude of metrics of interest to the designer (i.e. power, performance, temperature and reliability). In this dissertation we present a framework for multi-domain co-simulation and co-optimization of 3D CPU architectures with both air and MF cooling solutions. Finally we propose an approach for design space exploration and modeling within the new Co-Design paradigm, and discuss the possible avenues for improvement of this work in the future.