AIR SIDE HEAT TRANSFER ENHANCEMENT IN HEAT EXCHANGERS UTILIZING INNOVATIVE DESIGNS AND THE ADDITIVE MANUFACTURING TECHNIQUE

Over the last decade, rapid development of additive manufacturing techniques has allowed the fabrication of innovative and complex designs. One field that can benefit from such technology is heat exchanger fabrication, as heat exchanger design has become more and more complex due to the demand for higher performance particularly on the air side of the heat exchanger. By employing the additive manufacturing, a heat exchanger design was successfully realized, which otherwise would have been very difficult to fabricate using conventional fabrication technologies. In this dissertation, additive manufacturing technique was implemented to fabricate an advanced design which focused on a combination of heat transfer surface and fluid distribution system. Although the application selected in this dissertation is focused on power plant dry cooling applications, the results of this study can directly and indirectly benefit other sectors as well, as the air-side is often the limiting side for in liquid or single phase cooling applications. Two heat exchanger designs were studied. One was an advanced metallic heat exchanger based on manifold-microchannel technology and the other was a polymer heat exchanger based on utilization of prime surface technology. Polymer heat exchangers offer several advantages over metals such as antifouling, anticorrosion, lightweight and often less expensive than comparable metallic heat exchangers. A numerical modeling and optimization were performed to calculate a design that yield an optimum performance. The optimization results show that significant performance enhancement is noted compared to the conventional heat exchangers like wavy fins and plain plate fins. Thereafter, both heat exchangers were scaled down and fabricated using additive manufacturing and experimentally tested. The manifold-micro channel design demonstrated that despite some fabrication inaccuracies, compared to a conventional wavy-fin surface, 15% - 50% increase in heat transfer coefficient was possible for the same pressure drop value. In addition, if the fabrication inaccuracy can be eliminated, an even larger performance enhancement is predicted. Since metal based additive manufacturing is still in the developmental stage, it is anticipated that with further refinement of the manufacturing process in future designs, the fabrication accuracy can be improved. For the polymer heat exchanger, by fabricating a very thin wall heat exchanger (150μm), the wall thermal resistance, which usually becomes the limiting side for polymer heat exchanger, was calculated to account for only up to 3% of the total thermal resistance. A comparison of air-side heat transfer coefficient of the polymer heat exchanger with some of the commercially available plain plate fin surface heat exchangers show that polymer heat exchanger performance is equal or superior to plain plate fin surfaces. This shows the promising potential for polymer heat exchangers to compete with conventional metallic heat exchangers when an additive manufacturing-enabled fabrication is utilized. Major contributions of this study are as follows: (1) For the first time demonstrated the potential of additive manufacturing in metal printing of heat exchangers that benefit from a sophisticated design to yield a performance substantially above the respective conventional systems. Such heat exchangers cannot be fabricated with the conventional fabrication techniques. (2) For the first time demonstrated the potential of additive manufacturing to produce polymer heat exchangers that by design minimize the role of thermal conductivity and deliver a thermal performance equal or better that their respective metallic heat exchangers. In addition of other advantages of polymer over metal like antifouling, anticorrosion, and lightweight. Details of the work are documented in respective chapters of this thesis.

DESIGN, FABRICATION, AND PERFORMANCE CHARACTERIZATION OF MULTIFUNCTIONAL STRUCTURES TO HARVEST SOLAR ENERGY FOR FLAPPING WING AERIAL VEHICLES

Flapping Wing Aerial Vehicles (FWAVs) have the capability to combine the benefits of both fixed wing vehicles and rotary vehicles. However, flight time is limited due to limited on-board energy storage capacity. For most Unmanned Aerial Vehicle (UAV) operators, frequent recharging of the batteries is not ideal due to lack of nearby electrical outlets. This imposes serious limitations on FWAV flights. The approach taken to extend the flight time of UAVs was to integrate photovoltaic solar cells onto different structures of the vehicle to harvest and use energy from the sun. Integration of the solar cells can greatly improve the energy capacity of an UAV; however, this integration does effect the performance of the UAV and especially FWAVs. The integration of solar cells affects the ability of the vehicle to produce the aerodynamic forces necessary to maintain flight. This PhD dissertation characterizes the effects of solar cell integration on the performance of a FWAV. Robo Raven, a recently developed FWAV, is used as the platform for this work. An additive manufacturing technique was developed to integrate photovoltaic solar cells into the wing and tail structures of the vehicle. An approach to characterizing the effects of solar cell integration to the wings, tail, and body of the UAV is also described. This approach includes measurement of aerodynamic forces generated by the vehicle and measurements of the wing shape during the flapping cycle using Digital Image Correlation. Various changes to wing, body, and tail design are investigated and changes in performance for each design are measured. The electrical performance from the solar cells is also characterized. A new multifunctional performance model was formulated that describes how integration of solar cells influences the flight performance. Aerodynamic models were developed to describe effects of solar cell integration force production and performance of the FWAV. Thus, performance changes can be predicted depending on changes in design. Sensing capabilities of the solar cells were also discovered and correlated to the deformation of the wing. This demonstrated that the solar cells were capable of: (1) Lightweight and flexible structure to generate aerodynamic forces, (2) Energy harvesting to extend operational time and autonomy, (3) Sensing of an aerodynamic force associated with wing deformation. Finally, different flexible photovoltaic materials with higher efficiencies are investigated, which enable the multifunctional wings to provide enough solar power to keep the FWAV aloft without batteries as long as there is enough sunlight to power the vehicle.

Thermal Tracking and Estimation for Microprocessors

Due to increasing integration density and operating frequency of today's high performance processors, the temperature of a typical chip can easily exceed 100 degrees Celsius. However, the runtime thermal state of a chip is very hard to predict and manage due to the random nature in computing workloads, as well as the process, voltage and ambient temperature variability (together called PVT variability). The uneven nature (both in time and space) of the heat dissipation of the chip could lead to severe reliability issues and error-prone chip behavior (e.g. timing errors). Many dynamic power/thermal management techniques have been proposed to address this issue such as dynamic voltage and frequency scaling (DVFS), clock gating and etc. However, most of such techniques require accurate knowledge of the runtime thermal state of the chip to make efficient and effective control decisions. In this work we address the problem of tracking and managing the temperature of microprocessors which include the following sub-problems: (1) how to design an efficient sensor-based thermal tracking system on a given design that could provide accurate real-time temperature feedback; (2) what statistical techniques could be used to estimate the full-chip thermal profile based on very limited (and possibly noise-corrupted) sensor observations; (3) how do we adapt to changes in the underlying system's behavior, since such changes could impact the accuracy of our thermal estimation. The thermal tracking methodology proposed in this work is enabled by on-chip sensors which are already implemented in many modern processors. We first investigate the underlying relationship between heat distribution and power consumption, then we introduce an accurate thermal model for the chip system. Based on this model, we characterize the temperature correlation that exists among different chip modules and explore statistical approaches (such as those based on Kalman filter) that could utilize such correlation to estimate the accurate chip-level thermal profiles in real time. Such estimation is performed based on limited sensor information because sensors are usually resource constrained and noise-corrupted. We also took a further step to extend the standard Kalman filter approach to account for (1) nonlinear effects such as leakage-temperature interdependency and (2) varying statistical characteristics in the underlying system model. The proposed thermal tracking infrastructure and estimation algorithms could consistently generate accurate thermal estimates even when the system is switching among workloads that have very distinct characteristics. Through experiments, our approaches have demonstrated promising results with much higher accuracy compared to existing approaches. Such results can be used to ensure thermal reliability and improve the effectiveness of dynamic thermal management techniques.

Architectural-Physical Co-Design of 3D CPUs with Micro-Fluidic Cooling

The performance, energy efficiency and cost improvements due to traditional technology scaling have begun to slow down and present diminishing returns. Underlying reasons for this trend include fundamental physical limits of transistor scaling, the growing significance of quantum effects as transistors shrink, and a growing mismatch between transistors and interconnects regarding size, speed and power. Continued Moore's Law scaling will not come from technology scaling alone, and must involve improvements to design tools and development of new disruptive technologies such as 3D integration. 3D integration presents potential improvements to interconnect power and delay by translating the routing problem into a third dimension, and facilitates transistor density scaling independent of technology node. Furthermore, 3D IC technology opens up a new architectural design space of heterogeneously-integrated high-bandwidth CPUs. Vertical integration promises to provide the CPU architectures of the future by integrating high performance processors with on-chip high-bandwidth memory systems and highly connected network-on-chip structures. Such techniques can overcome the well-known CPU performance bottlenecks referred to as memory and communication wall. However the promising improvements to performance and energy efficiency offered by 3D CPUs does not come without cost, both in the financial investments to develop the technology, and the increased complexity of design. Two main limitations to 3D IC technology have been heat removal and TSV reliability. Transistor stacking creates increases in power density, current density and thermal resistance in air cooled packages. Furthermore the technology introduces vertical through silicon vias (TSVs) that create new points of failure in the chip and require development of new BEOL technologies. Although these issues can be controlled to some extent using thermal-reliability aware physical and architectural 3D design techniques, high performance embedded cooling schemes, such as micro-fluidic (MF) cooling, are fundamentally necessary to unlock the true potential of 3D ICs. A new paradigm is being put forth which integrates the computational, electrical, physical, thermal and reliability views of a system. The unification of these diverse aspects of integrated circuits is called Co-Design. Independent design and optimization of each aspect leads to sub-optimal designs due to a lack of understanding of cross-domain interactions and their impacts on the feasibility region of the architectural design space. Co-Design enables optimization across layers with a multi-domain view and thus unlocks new high-performance and energy efficient configurations. Although the co-design paradigm is becoming increasingly necessary in all fields of IC design, it is even more critical in 3D ICs where, as we show, the inter-layer coupling and higher degree of connectivity between components exacerbates the interdependence between architectural parameters, physical design parameters and the multitude of metrics of interest to the designer (i.e. power, performance, temperature and reliability). In this dissertation we present a framework for multi-domain co-simulation and co-optimization of 3D CPU architectures with both air and MF cooling solutions. Finally we propose an approach for design space exploration and modeling within the new Co-Design paradigm, and discuss the possible avenues for improvement of this work in the future.

Physical Design Methodologies for Low Power and Reliable 3D ICs

As the semiconductor industry struggles to maintain its momentum down the path following the Moore's Law, three dimensional integrated circuit (3D IC) technology has emerged as a promising solution to achieve higher integration density, better performance, and lower power consumption. However, despite its significant improvement in electrical performance, 3D IC presents several serious physical design challenges. In this dissertation, we investigate physical design methodologies for 3D ICs with primary focus on two areas: low power 3D clock tree design, and reliability degradation modeling and management. Clock trees are essential parts for digital system which dissipate a large amount of power due to high capacitive loads. The majority of existing 3D clock tree designs focus on minimizing the total wire length, which produces sub-optimal results for power optimization. In this dissertation, we formulate a 3D clock tree design flow which directly optimizes for clock power. Besides, we also investigate the design methodology for clock gating a 3D clock tree, which uses shutdown gates to selectively turn off unnecessary clock activities. Different from the common assumption in 2D ICs that shutdown gates are cheap thus can be applied at every clock node, shutdown gates in 3D ICs introduce additional control TSVs, which compete with clock TSVs for placement resources. We explore the design methodologies to produce the optimal allocation and placement for clock and control TSVs so that the clock power is minimized. We show that the proposed synthesis flow saves significant clock power while accounting for available TSV placement area. Vertical integration also brings new reliability challenges including TSV's electromigration (EM) and several other reliability loss mechanisms caused by TSV-induced stress. These reliability loss models involve complex inter-dependencies between electrical and thermal conditions, which have not been investigated in the past. In this dissertation we set up an electrical/thermal/reliability co-simulation framework to capture the transient of reliability loss in 3D ICs. We further derive and validate an analytical reliability objective function that can be integrated into the 3D placement design flow. The reliability aware placement scheme enables co-design and co-optimization of both the electrical and reliability property, thus improves both the circuit's performance and its lifetime. Our electrical/reliability co-design scheme avoids unnecessary design cycles or application of ad-hoc fixes that lead to sub-optimal performance. Vertical integration also enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. In addition, a dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance. The proposed physical design methodologies should act as important building blocks for 3D ICs and push 3D ICs toward mainstream acceptance in the near future.

A Thermal Management Solution for Compact Power Converters

Regulated Transformer Rectifier Units contain several power electronic boards to facilitate AC to DC power conversion. As these units become smaller, the number of devices on each board increases while their distance from each other decreases, making active cooling essential to maintaining reliable operation. Although it is widely accepted that liquid is a far superior heat transfer medium to air, the latter is still capable of yielding low device operating temperatures with proper heat sink and airflow design. The purpose of this study is to describe the models and methods used to design and build the thermal management system for one of the power electronic boards in a compact, high power regulated transformer rectifier unit. Maximum device temperature, available pressure drop and manufacturability were assessed when selecting the final design for testing. Once constructed, the thermal management system’s performance was experimentally verified at three different power levels.