Security through Obscurity: Layout Obfuscation of Digital Integrated Circuits using Don't Care Conditions

Contemporary integrated circuits are designed and manufactured in a globalized environment leading to concerns of piracy, overproduction and counterfeiting. One class of techniques to combat these threats is circuit obfuscation which seeks to modify the gate-level (or structural) description of a circuit without affecting its functionality in order to increase the complexity and cost of reverse engineering. Most of the existing circuit obfuscation methods are based on the insertion of additional logic (called “key gates”) or camouflaging existing gates in order to make it difficult for a malicious user to get the complete layout information without extensive computations to determine key-gate values. However, when the netlist or the circuit layout, although camouflaged, is available to the attacker, he/she can use advanced logic analysis and circuit simulation tools and Boolean SAT solvers to reveal the unknown gate-level information without exhaustively trying all the input vectors, thus bringing down the complexity of reverse engineering. To counter this problem, some ‘provably secure’ logic encryption algorithms that emphasize methodical selection of camouflaged gates have been proposed previously in literature [1,2,3]. The contribution of this paper is the creation and simulation of a new layout obfuscation method that uses don't care conditions. We also present proof-of-concept of a new functional or logic obfuscation technique that not only conceals, but modifies the circuit functionality in addition to the gate-level description, and can be implemented automatically during the design process. Our layout obfuscation technique utilizes don’t care conditions (namely, Observability and Satisfiability Don’t Cares) inherent in the circuit to camouflage selected gates and modify sub-circuit functionality while meeting the overall circuit specification. Here, camouflaging or obfuscating a gate means replacing the candidate gate by a 4X1 Multiplexer which can be configured to perform all possible 2-input/ 1-output functions as proposed by Bao et al. [4]. It is important to emphasize that our approach not only obfuscates but alters sub-circuit level functionality in an attempt to make IP piracy difficult. The choice of gates to obfuscate determines the effort required to reverse engineer or brute force the design. As such, we propose a method of camouflaged gate selection based on the intersection of output logic cones. By choosing these candidate gates methodically, the complexity of reverse engineering can be made exponential, thus making it computationally very expensive to determine the true circuit functionality. We propose several heuristic algorithms to maximize the RE complexity based on don’t care based obfuscation and methodical gate selection. Thus, the goal of protecting the design IP from malicious end-users is achieved. It also makes it significantly harder for rogue elements in the supply chain to use, copy or replicate the same design with a different logic. We analyze the reverse engineering complexity by applying our obfuscation algorithm on ISCAS-85 benchmarks. Our experimental results indicate that significant reverse engineering complexity can be achieved at minimal design overhead (average area overhead for the proposed layout obfuscation methods is 5.51% and average delay overhead is about 7.732%). We discuss the strengths and limitations of our approach and suggest directions that may lead to improved logic encryption algorithms in the future. References: [1] R. Chakraborty and S. Bhunia, “HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493–1502, 2009. [2] J. A. Roy, F. Koushanfar, and I. L. Markov, “EPIC: Ending Piracy of Integrated Circuits,” in 2008 Design, Automation and Test in Europe, 2008, pp. 1069–1074. [3] J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, “Security Analysis of Integrated Circuit Camouflaging,” ACM Conference on Computer Communications and Security, 2013. [4] Bao Liu, Wang, B., "Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks,"Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , vol., no., pp.1,6, 24-28 March 2014.

Understanding the Reaction Mechanism of Nanocomposite Thermites

Nanocomposite energetics are a relatively new class of materials that combine nanoscale fuels and oxidizers to allow for the rapid release of large amounts of energy. In thermite systems (metal fuel with metal oxide oxidizer), the use of nanomaterials has been illustrated to increase reactivity by multiple orders of magnitude as a result of the higher specific surface area and smaller diffusion length scales. However, the highly dynamic and nanoscale processes intrinsic to these materials, as well as heating rate dependencies, have limited our understanding of the underlying processes that control reaction and propagation. For my dissertation, I have employed a variety of experimental approaches that have allowed me to probe these processes at heating rates representative of free combustion with the goal of understanding the fundamental mechanisms. Dynamic transmission electron microscopy (DTEM) was used to study the in situ morphological change that occurs in nanocomposite thermite materials subjected to rapid (10^11 K/s) heating. Aluminum nanoparticle (Al-NP) aggregates were found to lose their nanostructure through coalescence in as little as 10 ns, which is much faster than any other timescale of combustion. Further study of nanoscale reaction with CuO determined that a condensed phase interfacial reaction could occur within 0.5-5 µs in a manner consistent with bulk reaction, which supports that this mechanism plays a dominant role in the overall reaction process. Ta nanocomposites were also studied to determine if a high melting point (3280 K) affects the loss of nanostructure and rate of reaction. The condensed phase reaction pathway was further explored using reactive multilayers sputter deposited onto thin Pt wires to allow for temperature jump (T-Jump) heating at rates of ~5x10^5 K/s. High speed video and a time of flight mass spectrometry (TOFMS) were used to observe ignition temperature and speciation as a function of bilayer thickness. The ignition process was modeled and a low activation energy for effective diffusivity was determined. T-Jump TOFMS along with constant volume combustion cell studies were also used to determine the effect of gas release in nanoparticle systems by comparing the reaction properties of CuO and Cu2O.