AIR SIDE HEAT TRANSFER ENHANCEMENT IN HEAT EXCHANGERS UTILIZING INNOVATIVE DESIGNS AND THE ADDITIVE MANUFACTURING TECHNIQUE

Over the last decade, rapid development of additive manufacturing techniques has allowed the fabrication of innovative and complex designs. One field that can benefit from such technology is heat exchanger fabrication, as heat exchanger design has become more and more complex due to the demand for higher performance particularly on the air side of the heat exchanger. By employing the additive manufacturing, a heat exchanger design was successfully realized, which otherwise would have been very difficult to fabricate using conventional fabrication technologies. In this dissertation, additive manufacturing technique was implemented to fabricate an advanced design which focused on a combination of heat transfer surface and fluid distribution system. Although the application selected in this dissertation is focused on power plant dry cooling applications, the results of this study can directly and indirectly benefit other sectors as well, as the air-side is often the limiting side for in liquid or single phase cooling applications. Two heat exchanger designs were studied. One was an advanced metallic heat exchanger based on manifold-microchannel technology and the other was a polymer heat exchanger based on utilization of prime surface technology. Polymer heat exchangers offer several advantages over metals such as antifouling, anticorrosion, lightweight and often less expensive than comparable metallic heat exchangers. A numerical modeling and optimization were performed to calculate a design that yield an optimum performance. The optimization results show that significant performance enhancement is noted compared to the conventional heat exchangers like wavy fins and plain plate fins. Thereafter, both heat exchangers were scaled down and fabricated using additive manufacturing and experimentally tested. The manifold-micro channel design demonstrated that despite some fabrication inaccuracies, compared to a conventional wavy-fin surface, 15% - 50% increase in heat transfer coefficient was possible for the same pressure drop value. In addition, if the fabrication inaccuracy can be eliminated, an even larger performance enhancement is predicted. Since metal based additive manufacturing is still in the developmental stage, it is anticipated that with further refinement of the manufacturing process in future designs, the fabrication accuracy can be improved. For the polymer heat exchanger, by fabricating a very thin wall heat exchanger (150μm), the wall thermal resistance, which usually becomes the limiting side for polymer heat exchanger, was calculated to account for only up to 3% of the total thermal resistance. A comparison of air-side heat transfer coefficient of the polymer heat exchanger with some of the commercially available plain plate fin surface heat exchangers show that polymer heat exchanger performance is equal or superior to plain plate fin surfaces. This shows the promising potential for polymer heat exchangers to compete with conventional metallic heat exchangers when an additive manufacturing-enabled fabrication is utilized. Major contributions of this study are as follows: (1) For the first time demonstrated the potential of additive manufacturing in metal printing of heat exchangers that benefit from a sophisticated design to yield a performance substantially above the respective conventional systems. Such heat exchangers cannot be fabricated with the conventional fabrication techniques. (2) For the first time demonstrated the potential of additive manufacturing to produce polymer heat exchangers that by design minimize the role of thermal conductivity and deliver a thermal performance equal or better that their respective metallic heat exchangers. In addition of other advantages of polymer over metal like antifouling, anticorrosion, and lightweight. Details of the work are documented in respective chapters of this thesis.

Investigation into the Influence of Build Parameters on Failure of 3D Printed Parts

Additive manufacturing, including fused deposition modeling (FDM), is transforming the built world and engineering education. Deep understanding of parts created through FDM technology has lagged behind its adoption in home, work, and academic environments. Properties of parts created from bulk materials through traditional manufacturing are understood well enough to accurately predict their behavior through analytical models. Unfortunately, Additive Manufacturing (AM) process parameters create anisotropy on a scale that fundamentally affects the part properties. Understanding AM process parameters (implemented by program algorithms called slicers) is necessary to predict part behavior. Investigating algorithms controlling print parameters (slicers) revealed stark differences between the generation of part layers. In this work, tensile testing experiments, including a full factorial design, determined that three key factors, width, thickness, infill density, and their interactions, significantly affect the tensile properties of 3D printed test samples.

DESIGN, FABRICATION, AND PERFORMANCE CHARACTERIZATION OF MULTIFUNCTIONAL STRUCTURES TO HARVEST SOLAR ENERGY FOR FLAPPING WING AERIAL VEHICLES

Flapping Wing Aerial Vehicles (FWAVs) have the capability to combine the benefits of both fixed wing vehicles and rotary vehicles. However, flight time is limited due to limited on-board energy storage capacity. For most Unmanned Aerial Vehicle (UAV) operators, frequent recharging of the batteries is not ideal due to lack of nearby electrical outlets. This imposes serious limitations on FWAV flights. The approach taken to extend the flight time of UAVs was to integrate photovoltaic solar cells onto different structures of the vehicle to harvest and use energy from the sun. Integration of the solar cells can greatly improve the energy capacity of an UAV; however, this integration does effect the performance of the UAV and especially FWAVs. The integration of solar cells affects the ability of the vehicle to produce the aerodynamic forces necessary to maintain flight. This PhD dissertation characterizes the effects of solar cell integration on the performance of a FWAV. Robo Raven, a recently developed FWAV, is used as the platform for this work. An additive manufacturing technique was developed to integrate photovoltaic solar cells into the wing and tail structures of the vehicle. An approach to characterizing the effects of solar cell integration to the wings, tail, and body of the UAV is also described. This approach includes measurement of aerodynamic forces generated by the vehicle and measurements of the wing shape during the flapping cycle using Digital Image Correlation. Various changes to wing, body, and tail design are investigated and changes in performance for each design are measured. The electrical performance from the solar cells is also characterized. A new multifunctional performance model was formulated that describes how integration of solar cells influences the flight performance. Aerodynamic models were developed to describe effects of solar cell integration force production and performance of the FWAV. Thus, performance changes can be predicted depending on changes in design. Sensing capabilities of the solar cells were also discovered and correlated to the deformation of the wing. This demonstrated that the solar cells were capable of: (1) Lightweight and flexible structure to generate aerodynamic forces, (2) Energy harvesting to extend operational time and autonomy, (3) Sensing of an aerodynamic force associated with wing deformation. Finally, different flexible photovoltaic materials with higher efficiencies are investigated, which enable the multifunctional wings to provide enough solar power to keep the FWAV aloft without batteries as long as there is enough sunlight to power the vehicle.

Security through Obscurity: Layout Obfuscation of Digital Integrated Circuits using Don't Care Conditions

Contemporary integrated circuits are designed and manufactured in a globalized environment leading to concerns of piracy, overproduction and counterfeiting. One class of techniques to combat these threats is circuit obfuscation which seeks to modify the gate-level (or structural) description of a circuit without affecting its functionality in order to increase the complexity and cost of reverse engineering. Most of the existing circuit obfuscation methods are based on the insertion of additional logic (called “key gates”) or camouflaging existing gates in order to make it difficult for a malicious user to get the complete layout information without extensive computations to determine key-gate values. However, when the netlist or the circuit layout, although camouflaged, is available to the attacker, he/she can use advanced logic analysis and circuit simulation tools and Boolean SAT solvers to reveal the unknown gate-level information without exhaustively trying all the input vectors, thus bringing down the complexity of reverse engineering. To counter this problem, some ‘provably secure’ logic encryption algorithms that emphasize methodical selection of camouflaged gates have been proposed previously in literature [1,2,3]. The contribution of this paper is the creation and simulation of a new layout obfuscation method that uses don't care conditions. We also present proof-of-concept of a new functional or logic obfuscation technique that not only conceals, but modifies the circuit functionality in addition to the gate-level description, and can be implemented automatically during the design process. Our layout obfuscation technique utilizes don’t care conditions (namely, Observability and Satisfiability Don’t Cares) inherent in the circuit to camouflage selected gates and modify sub-circuit functionality while meeting the overall circuit specification. Here, camouflaging or obfuscating a gate means replacing the candidate gate by a 4X1 Multiplexer which can be configured to perform all possible 2-input/ 1-output functions as proposed by Bao et al. [4]. It is important to emphasize that our approach not only obfuscates but alters sub-circuit level functionality in an attempt to make IP piracy difficult. The choice of gates to obfuscate determines the effort required to reverse engineer or brute force the design. As such, we propose a method of camouflaged gate selection based on the intersection of output logic cones. By choosing these candidate gates methodically, the complexity of reverse engineering can be made exponential, thus making it computationally very expensive to determine the true circuit functionality. We propose several heuristic algorithms to maximize the RE complexity based on don’t care based obfuscation and methodical gate selection. Thus, the goal of protecting the design IP from malicious end-users is achieved. It also makes it significantly harder for rogue elements in the supply chain to use, copy or replicate the same design with a different logic. We analyze the reverse engineering complexity by applying our obfuscation algorithm on ISCAS-85 benchmarks. Our experimental results indicate that significant reverse engineering complexity can be achieved at minimal design overhead (average area overhead for the proposed layout obfuscation methods is 5.51% and average delay overhead is about 7.732%). We discuss the strengths and limitations of our approach and suggest directions that may lead to improved logic encryption algorithms in the future. References: [1] R. Chakraborty and S. Bhunia, “HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493–1502, 2009. [2] J. A. Roy, F. Koushanfar, and I. L. Markov, “EPIC: Ending Piracy of Integrated Circuits,” in 2008 Design, Automation and Test in Europe, 2008, pp. 1069–1074. [3] J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, “Security Analysis of Integrated Circuit Camouflaging,” ACM Conference on Computer Communications and Security, 2013. [4] Bao Liu, Wang, B., "Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks,"Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , vol., no., pp.1,6, 24-28 March 2014.

3D Ionospheric Effects on HF Propagation and Heating

The thesis uses a three-dimensional, first-principles model of the ionosphere in combination with High Frequency (HF) raytracing model to address key topics related to the physics of HF propagation and artificial ionospheric heating. In particular: 1. Explores the effect of the ubiquitous electron density gradients caused by Medium Scale Traveling Ionospheric Disturbances (MSTIDs) on high-angle of incidence HF radio wave propagation. Previous studies neglected the all-important presence of horizontal gradients in both the cross- and down-range directions, which refract the HF waves, significantly changing their path through the ionosphere. The physics-based ionosphere model SAMI3/ESF is used to generate a self-consistently evolving MSTID that allows for the examination of the spatio-temporal progression of the HF radio waves in the ionosphere. 2. Tests the potential and determines engineering requirements for ground- based high power HF heaters to trigger and control the evolution of Equatorial Spread F (ESF). Interference from ESF on radio wave propagation through the ionosphere remains a critical issue on HF systems reliability. Artificial HF heating has been shown to create plasma density cavities in the ionosphere similar to those that may trigger ESF bubbles. The work explores whether HF heating may trigger or control ESF bubbles. 3. Uses the combined ionosphere and HF raytracing models to create the first self-consistent HF Heating model. This model is utilized to simulate results from an Arecibo experiment and to provide understanding of the physical mechanism behind observed phenomena. The insights gained provide engineering guidance for new artificial heaters that are being built for use in low to middle latitude regions. In accomplishing the above topics: (i) I generated a model MSTID using the SAMI3/ESF code, and used a raytrace model to examine the effects of the MSTID gradients on radio wave propagation observables; (ii) I implemented a three- dimensional HF heating model in SAMI3/ESF and used the model to determine whether HF heating could artificially generate an ESF bubble; (iii) I created the first self-consistent model for artificial HF heating using the SAMI3/ESF ionosphere model and the MoJo raytrace model and ran a series of simulations that successfully modeled the results of early artificial heating experiments at Arecibo.

Engineering thin films of magnetic alloys and semiconductor oxides at the nanoscale

The thesis aims to exploit properties of thin films for applications such as spintronics, UV detection and gas sensing. Nanoscale thin films devices have myriad advantages and compatibility with Si-based integrated circuits processes. Two distinct classes of material systems are investigated, namely ferromagnetic thin films and semiconductor oxides. To aid the designing of devices, the surface properties of the thin films were investigated by using electron and photon characterization techniques including Auger electron spectroscopy (AES), X-ray photoelectron spectroscopy (XPS), grazing incidence X-ray diffraction (GIXRD), and energy-dispersive X-ray spectroscopy (EDS). These are complemented by nanometer resolved local proximal probes such as atomic force microscopy (AFM), magnetic force microscopy (MFM), electric force microscopy (EFM), and scanning tunneling microscopy to elucidate the interplay between stoichiometry, morphology, chemical states, crystallization, magnetism, optical transparency, and electronic properties. Specifically, I studied the effect of annealing on the surface stoichiometry of the CoFeB/Cu system by in-situ AES and discovered that magnetic nanoparticles with controllable areal density can be produced. This is a good alternative for producing nanoparticles using a maskless process. Additionally, I studied the behavior of magnetic domain walls of the low coercivity alloy CoFeB patterned nanowires. MFM measurement with the in-plane magnetic field showed that, compared to their permalloy counterparts, CoFeB nanowires require a much smaller magnetization switching field , making them promising for low-power-consumption domain wall motion based devices. With oxides, I studied CuO nanoparticles on SnO2 based UV photodetectors (PDs), and discovered that they promote the responsivity by facilitating charge transfer with the formed nanoheterojunctions. I also demonstrated UV PDs with spectrally tunable photoresponse with the bandgap engineered ZnMgO. The bandgap of the alloyed ZnMgO thin films was tailored by varying the Mg contents and AES was demonstrated as a surface scientific approach to assess the alloying of ZnMgO. With gas sensors, I discovered the rf-sputtered anatase-TiO2 thin films for a selective and sensitive NO2 detection at room temperature, under UV illumination. The implementation of UV enhances the responsivity, response and recovery rate of the TiO2 sensor towards NO2 significantly. Evident from the high resolution XPS and AFM studies, the surface contamination and morphology of the thin films degrade the gas sensing response. I also demonstrated that surface additive metal nanoparticles on thin films can improve the response and the selectivity of oxide based sensors. I employed nanometer-scale scanning probe microscopy to study a novel gas senor scheme consisting of gallium nitride (GaN) nanowires with functionalizing oxides layer. The results suggested that AFM together with EFM is capable of discriminating low-conductive materials at the nanoscale, providing a nondestructive method to quantitatively relate sensing response to the surface morphology.

Development of a Real-Time Hierarchical 3D Path Planning Algorithm for Unmanned Aerial Vehicles

Unmanned aerial vehicles (UAVs) frequently operate in partially or entirely unknown environments. As the vehicle traverses the environment and detects new obstacles, rapid path replanning is essential to avoid collisions. This thesis presents a new algorithm called Hierarchical D* Lite (HD*), which combines the incremental algorithm D* Lite with a novel hierarchical path planning approach to replan paths sufficiently fast for real-time operation. Unlike current hierarchical planning algorithms, HD* does not require map corrections before planning a new path. Directional cost scale factors, path smoothing, and Catmull-Rom splines are used to ensure the resulting paths are feasible. HD* sacrifices optimality for real-time performance. Its computation time and path quality are dependent on the map size, obstacle density, sensor range, and any restrictions on planning time. For the most complex scenarios tested, HD* found paths within 10% of optimal in under 35 milliseconds.

The Effect of Architecture and Shear Stress on Endothelialization of 3D Printed Vascular Networks

Despite significant progress in the field of tissue engineering within the last decade, a number of unsolved problems still remain. One of the most relevant issues is the lack of proper vascularization that limits the size of engineered tissues to smaller than clinically relevant dimensions. In particular, the growth of engineered tissue in vitro within bioreactors is plagued with this challenge. Specifically, the tubular perfusion system bioreactor has been used for large scale bone constructs; however these engineered constructs lack inherent vasculature and quickly develop a hypoxic core, where no nutrient exchange can occur, thus leading to cell death. Through the use of 3D printed vascular templates in conjunction with a tubular perfusion system bioreactor, we attempt to create an endothelial cell monolayer on 3D scaffolds that could potentially serve as the foundation of inherent vasculature within these engineered bone grafts.

Architectural-Physical Co-Design of 3D CPUs with Micro-Fluidic Cooling

The performance, energy efficiency and cost improvements due to traditional technology scaling have begun to slow down and present diminishing returns. Underlying reasons for this trend include fundamental physical limits of transistor scaling, the growing significance of quantum effects as transistors shrink, and a growing mismatch between transistors and interconnects regarding size, speed and power. Continued Moore's Law scaling will not come from technology scaling alone, and must involve improvements to design tools and development of new disruptive technologies such as 3D integration. 3D integration presents potential improvements to interconnect power and delay by translating the routing problem into a third dimension, and facilitates transistor density scaling independent of technology node. Furthermore, 3D IC technology opens up a new architectural design space of heterogeneously-integrated high-bandwidth CPUs. Vertical integration promises to provide the CPU architectures of the future by integrating high performance processors with on-chip high-bandwidth memory systems and highly connected network-on-chip structures. Such techniques can overcome the well-known CPU performance bottlenecks referred to as memory and communication wall. However the promising improvements to performance and energy efficiency offered by 3D CPUs does not come without cost, both in the financial investments to develop the technology, and the increased complexity of design. Two main limitations to 3D IC technology have been heat removal and TSV reliability. Transistor stacking creates increases in power density, current density and thermal resistance in air cooled packages. Furthermore the technology introduces vertical through silicon vias (TSVs) that create new points of failure in the chip and require development of new BEOL technologies. Although these issues can be controlled to some extent using thermal-reliability aware physical and architectural 3D design techniques, high performance embedded cooling schemes, such as micro-fluidic (MF) cooling, are fundamentally necessary to unlock the true potential of 3D ICs. A new paradigm is being put forth which integrates the computational, electrical, physical, thermal and reliability views of a system. The unification of these diverse aspects of integrated circuits is called Co-Design. Independent design and optimization of each aspect leads to sub-optimal designs due to a lack of understanding of cross-domain interactions and their impacts on the feasibility region of the architectural design space. Co-Design enables optimization across layers with a multi-domain view and thus unlocks new high-performance and energy efficient configurations. Although the co-design paradigm is becoming increasingly necessary in all fields of IC design, it is even more critical in 3D ICs where, as we show, the inter-layer coupling and higher degree of connectivity between components exacerbates the interdependence between architectural parameters, physical design parameters and the multitude of metrics of interest to the designer (i.e. power, performance, temperature and reliability). In this dissertation we present a framework for multi-domain co-simulation and co-optimization of 3D CPU architectures with both air and MF cooling solutions. Finally we propose an approach for design space exploration and modeling within the new Co-Design paradigm, and discuss the possible avenues for improvement of this work in the future.

Physical Design Methodologies for Low Power and Reliable 3D ICs

As the semiconductor industry struggles to maintain its momentum down the path following the Moore's Law, three dimensional integrated circuit (3D IC) technology has emerged as a promising solution to achieve higher integration density, better performance, and lower power consumption. However, despite its significant improvement in electrical performance, 3D IC presents several serious physical design challenges. In this dissertation, we investigate physical design methodologies for 3D ICs with primary focus on two areas: low power 3D clock tree design, and reliability degradation modeling and management. Clock trees are essential parts for digital system which dissipate a large amount of power due to high capacitive loads. The majority of existing 3D clock tree designs focus on minimizing the total wire length, which produces sub-optimal results for power optimization. In this dissertation, we formulate a 3D clock tree design flow which directly optimizes for clock power. Besides, we also investigate the design methodology for clock gating a 3D clock tree, which uses shutdown gates to selectively turn off unnecessary clock activities. Different from the common assumption in 2D ICs that shutdown gates are cheap thus can be applied at every clock node, shutdown gates in 3D ICs introduce additional control TSVs, which compete with clock TSVs for placement resources. We explore the design methodologies to produce the optimal allocation and placement for clock and control TSVs so that the clock power is minimized. We show that the proposed synthesis flow saves significant clock power while accounting for available TSV placement area. Vertical integration also brings new reliability challenges including TSV's electromigration (EM) and several other reliability loss mechanisms caused by TSV-induced stress. These reliability loss models involve complex inter-dependencies between electrical and thermal conditions, which have not been investigated in the past. In this dissertation we set up an electrical/thermal/reliability co-simulation framework to capture the transient of reliability loss in 3D ICs. We further derive and validate an analytical reliability objective function that can be integrated into the 3D placement design flow. The reliability aware placement scheme enables co-design and co-optimization of both the electrical and reliability property, thus improves both the circuit's performance and its lifetime. Our electrical/reliability co-design scheme avoids unnecessary design cycles or application of ad-hoc fixes that lead to sub-optimal performance. Vertical integration also enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. In addition, a dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance. The proposed physical design methodologies should act as important building blocks for 3D ICs and push 3D ICs toward mainstream acceptance in the near future.