Combined heat and power and campus carbon footprint reduction

Gemstone Team Cogeneration Technology

Why Does Employment Discrimination Persist against People with Mental Illness? Effects of Negative Stereotypes, Power, and Differential Discrimination

Mental illness affects a sizable minority of Americans at any given time, yet many people with mental illness (hereafter PWMI) remain unemployed or underemployed relative to the general population. Research has suggested that part of the reason for this is discrimination toward PWMI. This research investigated mechanisms that affect employment discrimination against PWMI. Drawing from theories on stigma and power, three studies assessed 1) the stereotyping of workers with mental illness as unfit for workplace success, 2) the impact of positive information on countering these negative stereotypes, and whether negatively-stereotyped conditions elicited discrimination; and 3) the effects of power on mental illness stigma components. I made a series of predictions related to theories on the Stereotype Content Model, illness attribution, the contact hypothesis, gender and mental health, and power. Studies tested predictions using, 1) an online vignette survey measuring attitudes, 2) an online survey measuring responses to fictitious applications for a middle management position, and 3) a laboratory experiment in which some participants were primed to feel powerful and some were not. Results of Study 1 demonstrated that PWMI were routinely stigmatized as incompetent, dangerous, and lacking valued employment attributes, relative to a control condition. This was especially evident for workers presented as having PTSD from wartime service and workers with schizophrenia, and when the worker was a woman. Study 2 showed that, although both war-related PTSD and schizophrenia evoke negative stereotypes, only schizophrenia evoked hiring discrimination. Finally, Study 3 found no effect of being primed to feel powerful on stigmatizing attitudes toward a person with symptoms of schizophrenia. Taken together, findings suggest that employment discrimination towards PWMI is driven by negative stereotypes; but, stereotypes might not lead to actual hiring discrimination for some labeled individuals.

Who Governs Educational Change? The Paradoxes of State Power and the Pursuit of Educational Reform in Post-Neoliberal Ecuador (2007-2015)

This study identifies and compares competing policy stories of key actors involved in the Ecuadorian education reform under President Rafael Correa from 2007-2015. By revealing these competing policy stories the study generates insights into the political and technical aspects of education reform in a context where state capacity has been eroded by decades of neoliberal policies. Since the elections in 2007, President Correa has focused much of his political effort and capital on reconstituting the state’s authority and capacity to not only formulate but also implement public policies. The concentration of power combined with a capacity building agenda allowed the Correa government to advance an ambitious comprehensive education reform with substantive results in equity and quality. At the same time the concentration of power has undermined a more inclusive and participatory approach which are essential for deepening and sustaining the reform. This study underscores both the limits and importance of state control over education; the inevitable conflicts and complexities associated with education reforms that focus on quality; and the limits and importance of participation in reform. Finally, it examines the analytical benefits of understanding governance, participation and quality as socially constructed concepts that are tied to normative and ideological interests.

Physical Design Methodologies for Low Power and Reliable 3D ICs

As the semiconductor industry struggles to maintain its momentum down the path following the Moore's Law, three dimensional integrated circuit (3D IC) technology has emerged as a promising solution to achieve higher integration density, better performance, and lower power consumption. However, despite its significant improvement in electrical performance, 3D IC presents several serious physical design challenges. In this dissertation, we investigate physical design methodologies for 3D ICs with primary focus on two areas: low power 3D clock tree design, and reliability degradation modeling and management. Clock trees are essential parts for digital system which dissipate a large amount of power due to high capacitive loads. The majority of existing 3D clock tree designs focus on minimizing the total wire length, which produces sub-optimal results for power optimization. In this dissertation, we formulate a 3D clock tree design flow which directly optimizes for clock power. Besides, we also investigate the design methodology for clock gating a 3D clock tree, which uses shutdown gates to selectively turn off unnecessary clock activities. Different from the common assumption in 2D ICs that shutdown gates are cheap thus can be applied at every clock node, shutdown gates in 3D ICs introduce additional control TSVs, which compete with clock TSVs for placement resources. We explore the design methodologies to produce the optimal allocation and placement for clock and control TSVs so that the clock power is minimized. We show that the proposed synthesis flow saves significant clock power while accounting for available TSV placement area. Vertical integration also brings new reliability challenges including TSV's electromigration (EM) and several other reliability loss mechanisms caused by TSV-induced stress. These reliability loss models involve complex inter-dependencies between electrical and thermal conditions, which have not been investigated in the past. In this dissertation we set up an electrical/thermal/reliability co-simulation framework to capture the transient of reliability loss in 3D ICs. We further derive and validate an analytical reliability objective function that can be integrated into the 3D placement design flow. The reliability aware placement scheme enables co-design and co-optimization of both the electrical and reliability property, thus improves both the circuit's performance and its lifetime. Our electrical/reliability co-design scheme avoids unnecessary design cycles or application of ad-hoc fixes that lead to sub-optimal performance. Vertical integration also enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. In addition, a dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance. The proposed physical design methodologies should act as important building blocks for 3D ICs and push 3D ICs toward mainstream acceptance in the near future.