Ceramic Materials Development for Intermediate Temperature Solid Oxide Fuel Cell (IT-SOFC)

Solid oxide fuel cell (SOFC) is an electrochemical device that converts chemical energy into electric power with high efficiency. Traditional SOFC has its disadvantages, such as redox cycling instability and carbon deposition while using hydrocarbon fuels. It is because traditional SOFC uses Ni-cermet as anode. In order to solve these problems, ceramic anode is a good candidate to replace Ni. However, the conductivity of most ceramic anode materials are much lower than Ni metal, and it introduces high ohmic resistance. How to increase the conductivity is a hot topic in this research field. Based on our proposed mechanism, several types of ceramic materials have been developed. Vanadium doped perovskite, Sr1-x/2VxTi1-xO3 (SVT) and Sr0.2Na0.8Nb1-xVxO3 (SNNV), achieved the conductivity as high as 300 S*cm-1 in hydrogen, without any high temperature reduction. GDC electrolyte supported cell was fabricated with Sr0.2Na0.8Nb0.9V0.1O3 and the performance was measured in hydrogen and methane respectively. Due to vanadium’s intrinsic problems, the anode supported cell is not easy. Fe doped double perovskite Sr2CoMoO6 (SFCM) was also developed. By carefully doping Fe, the conductivity was improved over one magnitude, without any vigorous reducing conditions. SFCM anode supported cell was successfully fabricated with GDC as the electrolyte. By impregnating Ni-GDC nano particles into the anode, the cell can be operated at lower temperatures while having higher performance than the traditional Ni-cermet cells. Meanwhile, this SFCM anode supported SOFC has long term stability in the reformate containing methane. During the anode development, cathode improvement caused by a thin Co-GDC layer was observed. By adding this Co-GDC layer between the electrolyte and the cathode, the interfacial resistance decreases due to fast oxygen ion transport. This mechanism was confirmed via isotope exchange. This Co-GDC layer works with multiple kinds of cathodes and the modified cell’s performance is 3 times as the traditional Ni-GDC cell. With this new method, lowering the SOFC operation temperature is feasible.

Architectural-Physical Co-Design of 3D CPUs with Micro-Fluidic Cooling

The performance, energy efficiency and cost improvements due to traditional technology scaling have begun to slow down and present diminishing returns. Underlying reasons for this trend include fundamental physical limits of transistor scaling, the growing significance of quantum effects as transistors shrink, and a growing mismatch between transistors and interconnects regarding size, speed and power. Continued Moore's Law scaling will not come from technology scaling alone, and must involve improvements to design tools and development of new disruptive technologies such as 3D integration. 3D integration presents potential improvements to interconnect power and delay by translating the routing problem into a third dimension, and facilitates transistor density scaling independent of technology node. Furthermore, 3D IC technology opens up a new architectural design space of heterogeneously-integrated high-bandwidth CPUs. Vertical integration promises to provide the CPU architectures of the future by integrating high performance processors with on-chip high-bandwidth memory systems and highly connected network-on-chip structures. Such techniques can overcome the well-known CPU performance bottlenecks referred to as memory and communication wall. However the promising improvements to performance and energy efficiency offered by 3D CPUs does not come without cost, both in the financial investments to develop the technology, and the increased complexity of design. Two main limitations to 3D IC technology have been heat removal and TSV reliability. Transistor stacking creates increases in power density, current density and thermal resistance in air cooled packages. Furthermore the technology introduces vertical through silicon vias (TSVs) that create new points of failure in the chip and require development of new BEOL technologies. Although these issues can be controlled to some extent using thermal-reliability aware physical and architectural 3D design techniques, high performance embedded cooling schemes, such as micro-fluidic (MF) cooling, are fundamentally necessary to unlock the true potential of 3D ICs. A new paradigm is being put forth which integrates the computational, electrical, physical, thermal and reliability views of a system. The unification of these diverse aspects of integrated circuits is called Co-Design. Independent design and optimization of each aspect leads to sub-optimal designs due to a lack of understanding of cross-domain interactions and their impacts on the feasibility region of the architectural design space. Co-Design enables optimization across layers with a multi-domain view and thus unlocks new high-performance and energy efficient configurations. Although the co-design paradigm is becoming increasingly necessary in all fields of IC design, it is even more critical in 3D ICs where, as we show, the inter-layer coupling and higher degree of connectivity between components exacerbates the interdependence between architectural parameters, physical design parameters and the multitude of metrics of interest to the designer (i.e. power, performance, temperature and reliability). In this dissertation we present a framework for multi-domain co-simulation and co-optimization of 3D CPU architectures with both air and MF cooling solutions. Finally we propose an approach for design space exploration and modeling within the new Co-Design paradigm, and discuss the possible avenues for improvement of this work in the future.

Combined heat and power and campus carbon footprint reduction

Gemstone Team Cogeneration Technology