School Development in Urbanizing Areas

Good schools are essential for building thriving urban areas. They are important for preparing the future human resource and directly contribute to social and economic development of a place. They not only act as magnets for prospective residents, but also are necessary for retaining current population. As public infrastructure, schools mirror their neighborhood. “Their location, design and physical condition are important determinants of neighborhood quality, regional growth and change, and quality of life.”2 They impact housing development and utility requirements among many things. Hence, planning for schools along with other infrastructure in an area is essential. Schools are very challenging to plan, especially in urbanizing areas with changing demographic dynamics, where the development market and housing development can shift drastically a number of times. In such places projecting the future school enrollments is very difficult and in case of large population influx, school development can be unable to catch up with population growth which results in overcrowding. Typical is the case of Arlington County VA. In the past two decades the County has changed dramatically from a collection of bedroom communities in Washington DC Metro Region to a thriving urban area. Its metro accessible urban corridors are among most desired locations for development in the region. However, converting single family neighborhoods into high density areas has put a lot of pressure on its school facilities and has resulted in overcrowded schools. Its public school enrollment has grown by 19% from 2009 to 2014.3 While the percentage of population under 5 years age has increased in last 10 years, those in the 5-19 age group have decreased4. Hence, there is more pressure on the elementary school facilities than others in the County. Design-wise, elementary schools, due to their size, can be imagined as a community component. There are a number of strategies that can be used to develop elementary school in urbanizing areas as a part of the neighborhood. Experimenting with space planning and building on partnership and mixed-use opportunities can help produce better designs for new schools in future. This thesis is an attempt to develop elementary school models for urbanizing areas of Arlington County. The school models will be designed keeping in mind the shifting nature of population and resulting student enrollments in these areas. They will also aim to be efficient and sustainable, and lead to the next generation design for elementary school education. The overall purpose of the project is to address barriers to elementary school development in urbanizing areas through creative design and planning strategies. To test above mentioned ideas, the Joint-Use School typology of housing +school design has been identified for elementary school development in urbanizing areas in this thesis project. The development is based on the Arlington Public School’s Program guidelines (catering to 600 students). The site selected for this project is Clarendon West (part of Red Top Cab Properties) in Clarendon, Arlington County VA.

Reclaiming the Fall Zone: Mediating Physical and Cultural Exchange in Richmond, VA

This thesis will address cultural and physical place reclamation, at the ambiguous intersection of ‘city’ and nature.’ By creating a juxtaposed sequence of multi-scalar interventions, which challenge the conventional boundaries of architecture, and landscape architecture; in order to make commonplace a new dynamic threshold condition in Richmond, Virginia. At its core, this thesis is an attempt at place-making on a site which has become ‘no place.’ This concept will be manifest via a landscape park on Mayo Island in Richmond, anchored by a community retreat center, and architectural follies along a constructed path. The interventions will coincide with value of place in historical Richmond: an integrated, socially desegregated waterfront hinge; a social nexus of inherent change, at the point which the river itself changes at the fall line.

Physical Design Methodologies for Low Power and Reliable 3D ICs

As the semiconductor industry struggles to maintain its momentum down the path following the Moore's Law, three dimensional integrated circuit (3D IC) technology has emerged as a promising solution to achieve higher integration density, better performance, and lower power consumption. However, despite its significant improvement in electrical performance, 3D IC presents several serious physical design challenges. In this dissertation, we investigate physical design methodologies for 3D ICs with primary focus on two areas: low power 3D clock tree design, and reliability degradation modeling and management. Clock trees are essential parts for digital system which dissipate a large amount of power due to high capacitive loads. The majority of existing 3D clock tree designs focus on minimizing the total wire length, which produces sub-optimal results for power optimization. In this dissertation, we formulate a 3D clock tree design flow which directly optimizes for clock power. Besides, we also investigate the design methodology for clock gating a 3D clock tree, which uses shutdown gates to selectively turn off unnecessary clock activities. Different from the common assumption in 2D ICs that shutdown gates are cheap thus can be applied at every clock node, shutdown gates in 3D ICs introduce additional control TSVs, which compete with clock TSVs for placement resources. We explore the design methodologies to produce the optimal allocation and placement for clock and control TSVs so that the clock power is minimized. We show that the proposed synthesis flow saves significant clock power while accounting for available TSV placement area. Vertical integration also brings new reliability challenges including TSV's electromigration (EM) and several other reliability loss mechanisms caused by TSV-induced stress. These reliability loss models involve complex inter-dependencies between electrical and thermal conditions, which have not been investigated in the past. In this dissertation we set up an electrical/thermal/reliability co-simulation framework to capture the transient of reliability loss in 3D ICs. We further derive and validate an analytical reliability objective function that can be integrated into the 3D placement design flow. The reliability aware placement scheme enables co-design and co-optimization of both the electrical and reliability property, thus improves both the circuit's performance and its lifetime. Our electrical/reliability co-design scheme avoids unnecessary design cycles or application of ad-hoc fixes that lead to sub-optimal performance. Vertical integration also enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. In addition, a dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance. The proposed physical design methodologies should act as important building blocks for 3D ICs and push 3D ICs toward mainstream acceptance in the near future.