The effect of collagen organization on tensile strength loss in anterior cruciate ligament grafts post-reconstruction surgery

Gemstone Team LEGS

The Effect of Diet-Induced Obesity and Subsequent Weight Loss on Body Composition, Glucose Clearance, Metabolite Profile and Liver Amp-Activated Protein Kinase in Mice

Obesity, currently an epidemic, is a difficult disease to combat because it is marked by both a change in body weight and an underlying dysregulation in metabolism, making consistent weight loss challenging. We sought to elucidate this metabolic dysregulation resulting from diet-induced obesity (DIO) that persists through subsequent weight loss. We hypothesized that weight gain imparts a change in “metabolic set point” persisting through subsequent weight loss and that this modification may involve a persistent change in hepatic AMP-activated protein kinase (AMPK), a key energy-sensing enzyme in the body. To test these hypotheses, we tracked metabolic perturbations through this period, measuring changes in hepatic AMPK. To further understand the role of AMPK we used AICAR, an AMPK activator, following DIO. Our findings established a more dynamic metabolic model of DIO and subsequent weight loss. We observed hepatic AMPK elevation following weight loss, but AICAR administration without similar dieting was unsuccessful in improving metabolic dysregulation. Our findings provide an approach to modeling DIO and subsequent dieting that can be built upon in future studies and hopefully contribute to more effective long-term treatments of obesity.

FAMILY CHARACTERISTICS, STATE PROGRAM EFFECTIVENESS, AND REPORT OF INADEQUATE CARE AMONG FAMILIES OF YOUNG CHILDREN WITH HEARING LOSS

Approximately 1.6 per 1,000 newborns in the U.S. are born with hearing loss. Congenital hearing loss poses a risk to their speech, language, cognitive, and social-emotional development. Early detection and intervention can improve outcomes. Every state has an Early Hearing Detection and Intervention program (EHDI) to promote and track screening, audiological assessments and linkage to early intervention. However, a large percentage of children are “lost to system (LTS),” meaning that they did not receive recommended care or that it was not reported. This study used data from the 2009-2010 National Survey of Children with Special Health Care Needs and data from the 2011 EHDI Hearing Screening and Follow-Up Survey to examine how 1) family characteristics; 2) EHDI program effectiveness, as determined by LTS percentages; and 3) the family conditions of education and poverty are related to parental report of inadequate care. The sample comprised 684 children between the ages of 0 and 5 years with hearing loss. The results indicated that living in states with less effective EHDI programs was associated with an increased likelihood of not receiving early intervention services (EIS) and of reporting poor family-centered communication. Sibling classification was associated with both receipt of EIS and report of unmet need. Single mothers were less likely to report increased difficulties accessing care. Poor and less educated families, assessed separately, who lived in states with less effective EHDI programs, were more likely to report non-receipt of EIS and less likely to report unmet need as compared to similar families living in states with more effective programs. Poor families living in states with less effective programs were more likely to report less coordinated care than were poor families living in states with more effective programs. This study supports the conclusion that both family characteristics and the effectiveness of state programs affect quality of care outcomes. It appears that less effective state programs affect disadvantaged families’ service receipt report more than that of advantaged families. These findings are important because they may provide insights into the development of targeted efforts to improve the system of care for children with hearing loss.

Physical Design Methodologies for Low Power and Reliable 3D ICs

As the semiconductor industry struggles to maintain its momentum down the path following the Moore's Law, three dimensional integrated circuit (3D IC) technology has emerged as a promising solution to achieve higher integration density, better performance, and lower power consumption. However, despite its significant improvement in electrical performance, 3D IC presents several serious physical design challenges. In this dissertation, we investigate physical design methodologies for 3D ICs with primary focus on two areas: low power 3D clock tree design, and reliability degradation modeling and management. Clock trees are essential parts for digital system which dissipate a large amount of power due to high capacitive loads. The majority of existing 3D clock tree designs focus on minimizing the total wire length, which produces sub-optimal results for power optimization. In this dissertation, we formulate a 3D clock tree design flow which directly optimizes for clock power. Besides, we also investigate the design methodology for clock gating a 3D clock tree, which uses shutdown gates to selectively turn off unnecessary clock activities. Different from the common assumption in 2D ICs that shutdown gates are cheap thus can be applied at every clock node, shutdown gates in 3D ICs introduce additional control TSVs, which compete with clock TSVs for placement resources. We explore the design methodologies to produce the optimal allocation and placement for clock and control TSVs so that the clock power is minimized. We show that the proposed synthesis flow saves significant clock power while accounting for available TSV placement area. Vertical integration also brings new reliability challenges including TSV's electromigration (EM) and several other reliability loss mechanisms caused by TSV-induced stress. These reliability loss models involve complex inter-dependencies between electrical and thermal conditions, which have not been investigated in the past. In this dissertation we set up an electrical/thermal/reliability co-simulation framework to capture the transient of reliability loss in 3D ICs. We further derive and validate an analytical reliability objective function that can be integrated into the 3D placement design flow. The reliability aware placement scheme enables co-design and co-optimization of both the electrical and reliability property, thus improves both the circuit's performance and its lifetime. Our electrical/reliability co-design scheme avoids unnecessary design cycles or application of ad-hoc fixes that lead to sub-optimal performance. Vertical integration also enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. In addition, a dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance. The proposed physical design methodologies should act as important building blocks for 3D ICs and push 3D ICs toward mainstream acceptance in the near future.