Time Reversed Electromagnetic Wave Propagation as a Novel Method of Wireless Power Transfer

We investigate the application of time-reversed electromagnetic wave propagation to transmit energy in a wireless power transmission system. “Time reversal” is a signal focusing method that exploits the time reversal invariance of the lossless wave equation to direct signals onto a single point inside a complex scattering environment. In this work, we explore the properties of time reversed microwave pulses in a low-loss ray-chaotic chamber. We measure the spatial profile of the collapsing wavefront around the target antenna, and demonstrate that time reversal can be used to transfer energy to a receiver in motion. We demonstrate how nonlinear elements can be controlled to selectively focus on one target out of a group. Finally, we discuss the design of a rectenna for use in a time reversal system. We explore the implication of these results, and how they may be applied in future technologies.

COMPREHENSIVE ELECTRICAL/OPTICAL/THERMAL CHARACTERIZATIONS OF HIGH POWER LIGHT EMITTING DIODES AND LASER DIODES

Thermal characterizations of high power light emitting diodes (LEDs) and laser diodes (LDs) are one of the most critical issues to achieve optimal performance such as center wavelength, spectrum, power efficiency, and reliability. Unique electrical/optical/thermal characterizations are proposed to analyze the complex thermal issues of high power LEDs and LDs. First, an advanced inverse approach, based on the transient junction temperature behavior, is proposed and implemented to quantify the resistance of the die-attach thermal interface (DTI) in high power LEDs. A hybrid analytical/numerical model is utilized to determine an approximate transient junction temperature behavior, which is governed predominantly by the resistance of the DTI. Then, an accurate value of the resistance of the DTI is determined inversely from the experimental data over the predetermined transient time domain using numerical modeling. Secondly, the effect of junction temperature on heat dissipation of high power LEDs is investigated. The theoretical aspect of junction temperature dependency of two major parameters – the forward voltage and the radiant flux – on heat dissipation is reviewed. Actual measurements of the heat dissipation over a wide range of junction temperatures are followed to quantify the effect of the parameters using commercially available LEDs. An empirical model of heat dissipation is proposed for applications in practice. Finally, a hybrid experimental/numerical method is proposed to predict the junction temperature distribution of a high power LD bar. A commercial water-cooled LD bar is used to present the proposed method. A unique experimental setup is developed and implemented to measure the average junction temperatures of the LD bar. After measuring the heat dissipation of the LD bar, the effective heat transfer coefficient of the cooling system is determined inversely. The characterized properties are used to predict the junction temperature distribution over the LD bar under high operating currents. The results are presented in conjunction with the wall-plug efficiency and the center wavelength shift.

Physical Design Methodologies for Low Power and Reliable 3D ICs

As the semiconductor industry struggles to maintain its momentum down the path following the Moore's Law, three dimensional integrated circuit (3D IC) technology has emerged as a promising solution to achieve higher integration density, better performance, and lower power consumption. However, despite its significant improvement in electrical performance, 3D IC presents several serious physical design challenges. In this dissertation, we investigate physical design methodologies for 3D ICs with primary focus on two areas: low power 3D clock tree design, and reliability degradation modeling and management. Clock trees are essential parts for digital system which dissipate a large amount of power due to high capacitive loads. The majority of existing 3D clock tree designs focus on minimizing the total wire length, which produces sub-optimal results for power optimization. In this dissertation, we formulate a 3D clock tree design flow which directly optimizes for clock power. Besides, we also investigate the design methodology for clock gating a 3D clock tree, which uses shutdown gates to selectively turn off unnecessary clock activities. Different from the common assumption in 2D ICs that shutdown gates are cheap thus can be applied at every clock node, shutdown gates in 3D ICs introduce additional control TSVs, which compete with clock TSVs for placement resources. We explore the design methodologies to produce the optimal allocation and placement for clock and control TSVs so that the clock power is minimized. We show that the proposed synthesis flow saves significant clock power while accounting for available TSV placement area. Vertical integration also brings new reliability challenges including TSV's electromigration (EM) and several other reliability loss mechanisms caused by TSV-induced stress. These reliability loss models involve complex inter-dependencies between electrical and thermal conditions, which have not been investigated in the past. In this dissertation we set up an electrical/thermal/reliability co-simulation framework to capture the transient of reliability loss in 3D ICs. We further derive and validate an analytical reliability objective function that can be integrated into the 3D placement design flow. The reliability aware placement scheme enables co-design and co-optimization of both the electrical and reliability property, thus improves both the circuit's performance and its lifetime. Our electrical/reliability co-design scheme avoids unnecessary design cycles or application of ad-hoc fixes that lead to sub-optimal performance. Vertical integration also enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. In addition, a dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance. The proposed physical design methodologies should act as important building blocks for 3D ICs and push 3D ICs toward mainstream acceptance in the near future.

The Impact of Motor Learning on Motor Behavior and Cortical Dynamics in a Complex Stressful Social Environment

An economy of effort is a core characteristic of highly skilled motor performance often described as being effortless or automatic. Electroencephalographic (EEG) evaluation of cortical activity in elite performers has consistently revealed a reduction in extraneous associative cortical activity and an enhancement of task-relevant cortical processes. However, this has only been demonstrated under what are essentially practice-like conditions. Recently it has been shown that cerebral cortical activity becomes less efficient when performance occurs in a stressful, complex social environment. This dissertation examines the impact of motor skill training or practice on the EEG cortical dynamics that underlie performance in a stressful, complex social environment. Sixteen ROTC cadets participated in head-to-head pistol shooting competitions before and after completing nine sessions of skill training over three weeks. Spectral power increased in the theta frequency band and decreased in the low alpha frequency band after skill training. EEG Coherence increased in the left frontal region and decreased in the left temporal region after the practice intervention. These suggest a refinement of cerebral cortical dynamics with a reduction of task extraneous processing in the left frontal region and an enhancement of task related processing in the left temporal region consistent with the skill level reached by participants. Partitioning performance into ‘best’ and ‘worst’ based on shot score revealed that deliberate practice appears to optimize cerebral cortical activity of ‘best’ performances which are accompanied by a reduction in task-specific processes reflected by increased high-alpha power, while ‘worst’ performances are characterized by an inappropriate reduction in task-specific processing resulting in a loss of focus reflected by higher high-alpha power after training when compared to ‘best’ performances. Together, these studies demonstrate the power of experience afforded by practice, as a controllable factor, to promote resilience of cerebral cortical efficiency in complex environments.