Surface Insulation Resistance Degradation and Electrochemical Migration on Printed Circuit Boards

Widespread adoption of lead-free materials and processing for printed circuit board (PCB) assembly has raised reliability concerns regarding surface insulation resistance (SIR) degradation and electrochemical migration (ECM). As PCB conductor spacings decrease, electronic products become more susceptible to these failures mechanisms, especially in the presence of surface contamination and flux residues which might remain after no-clean processing. Moreover, the probability of failure due to SIR degradation and ECM is affected by the interaction between physical factors (such as temperature, relative humidity, electric field) and chemical factors (such as solder alloy, substrate material, no-clean processing). Current industry standards for assessing SIR reliability are designed to serve as short-term qualification tests, typically lasting 72 to 168 hours, and do not provide a prediction of reliability in long-term applications. The risk of electrochemical migration with lead-free assemblies has not been adequately investigated. Furthermore, the mechanism of electrochemical migration is not completely understood. For example, the role of path formation has not been discussed in previous studies. Another issue is that there are very few studies on development of rapid assessment methodologies for characterizing materials such as solder flux with respect to their potential for promoting ECM. In this dissertation, the following research accomplishments are described: 1). Long-term temp-humidity-bias (THB) testing over 8,000 hours assessing the reliability of printed circuit boards processed with a variety of lead-free solder pastes, solder pad finishes, and substrates. 2). Identification of silver migration from Sn3.5Ag and Sn3.0Ag0.5Cu lead-free solder, which is a completely new finding compared with previous research. 3). Established the role of path formation as a step in the ECM process, and provided clarification of the sequence of individual steps in the mechanism of ECM: path formation, electrodeposition, ion transport, electrodeposition, and filament formation. 4). Developed appropriate accelerated testing conditions for assessing the no-clean processed PCBs' susceptibility to ECM: a). Conductor spacings in test structures should be reduced in order to reflect the trend of higher density electronics and the effect of path formation, independent of electric field, on the time-to-failure. b). THB testing temperatures should be modified according to the material present on the PCB, since testing at 85oC can cause the evaporation of weak organic acids (WOAs) in the flux residues, leading one to underestimate the risk of ECM. 5). Correlated temp-humidity-bias testing with ion chromatography analysis and potentiostat measurement to develop an efficient and effective assessment methodology to characterize the effect of no-clean processing on ECM.

Advanced Adhesion Strength Testing Methods of Thin Film Multilayers in Electronic Packaging Systems

With the continued miniaturization and increasing performance of electronic devices, new technical challenges have arisen. One such issue is delamination occurring at critical interfaces inside the device. This major reliability issue can occur during the manufacturing process or during normal use of the device. Proper evaluation of the adhesion strength of critical interfaces early in the product development cycle can help reduce reliability issues and time-to-market of the product. However, conventional adhesion strength testing is inherently limited in the face of package miniaturization, which brings about further technical challenges to quantify design integrity and reliability. Although there are many different interfaces in today's advanced electronic packages, they can be generalized into two main categories: 1) rigid to rigid connections with a thin flexible polymeric layer in between, or 2) a thin film membrane on a rigid structure. Knowing that every technique has its own advantages and disadvantages, multiple testing methods must be enhanced and developed to be able to accommodate all the interfaces encountered for emerging electronic packaging technologies. For evaluating the adhesion strength of high adhesion strength interfaces in thin multilayer structures a novel adhesion test configuration called “single cantilever adhesion test (SCAT)” is proposed and implemented for an epoxy molding compound (EMC) and photo solder resist (PSR) interface. The test method is then shown to be capable of comparing and selecting the stronger of two potential EMC/PSR material sets. Additionally, a theoretical approach for establishing the applicable testing domain for a four-point bending test method was presented. For evaluating polymeric films on rigid substrates, major testing challenges are encountered for reducing testing scatter and for factoring in the potentially degrading effect of environmental conditioning on the material properties of the film. An advanced blister test with predefined area test method was developed that considers an elasto-plastic analytical solution and implemented for a conformal coating used to prevent tin whisker growth. The advanced blister testing with predefined area test method was then extended by employing a numerical method for evaluating the adhesion strength when the polymer’s film properties are unknown.

EFFECT OF ISOTHERMAL AGING ON SAC305 HARMONIC VIBRATION DURABILITY

The effect of isothermal aging on the harmonic vibration durability of Sn3.0Ag0.5Cu solder interconnects is examined. Printed wiring assemblies with daisy-chained leadless chip resistors (LCRs) are aged at 125°C for 0, 100, and 500 hours. These assemblies are instrumented with accelerometers and strain gages to maintain the same harmonic vibration profile in-test, and to characterize PWB behavior. The tested assemblies are excited at their first natural frequencies until LCRs show a resistance increase of 20%. Dynamic finite element models are employed to generate strain transfer functions, which relate board strain levels observed in-test to respective solder strain levels. The transfer functions are based on locally averaged values of strains in critical regions of the solder and in appropriate regions of the PWB. The vibration test data and the solder strains from FEA are used to estimate lower-bound material fatigue curves for SAC305 solder materials, as a function of isothermal pre-aging.

DEVELOPMENT OF AN OFF-LINE RAINFLOW COUNTING ALGORITHM WITH TEMPORAL PARAMETERS AND DATA REDUCTION

Rainflow counting methods convert a complex load time history into a set of load reversals for use in fatigue damage modeling. Rainflow counting methods were originally developed to assess fatigue damage associated with mechanical cycling where creep of the material under load was not considered to be a significant contributor to failure. However, creep is a significant factor in some cyclic loading cases such as solder interconnects under temperature cycling. In this case, fatigue life models require the dwell time to account for stress relaxation and creep. This study develops a new version of the multi-parameter rainflow counting algorithm that provides a range-based dwell time estimation for use with time-dependent fatigue damage models. To show the applicability, the method is used to calculate the life of solder joints under a complex thermal cycling regime and is verified by experimental testing. An additional algorithm is developed in this study to provide data reduction in the results of the rainflow counting. This algorithm uses a damage model and a statistical test to determine which of the resultant cycles are statistically insignificant to a given confidence level. This makes the resulting data file to be smaller, and for a simplified load history to be reconstructed.