Cultural and Social Cognitive Predictors of Academic Satisfaction in Southeast Asian American College Students

This study examined the predictive utility of Lent’s (2004) social cognitive model of well-being in the context of academic satisfaction with a sample of Southeast Asian American college students using a cross-sectional design. Path analysis was used to examine the role of perceived parental trauma, perceived parental acculturative stress, intergenerational family conflict, and social cognitive predictors to academic satisfaction. Participants were 111 Southeast Asian American and 111 East Asian American college students who completed online measures. Contrary to expectations, none of the contextual cultural variables were significant predictors of academic satisfaction. Also contrary to expectations, academic support and self-efficacy were not directly linked to academic satisfaction and outcome expectation was not linked to goal progress. Other social cognitive predictors were related directly and indirectly to academic satisfaction, consistent with prior research. Limitations and implications for future research and practice are addressed.

A Social Cognitive Approach to Coping with Acculturative Stress in International Students

The present study employed a cross-sectional design to test a model of coping with acculturative stress in an international student sample. Drawing from Lent’s (2004) social cognitive model of restorative well-being, several direct and mediated paths were hypothesized to predict (negatively) acculturative stress and (positively) life satisfaction. Behavioral acculturation and behavioral enculturation (Kim & Omizo, 2006) were also examined as predictors of coping with acculturative stress among international students. Using a self-report survey, participants’ ratings of acculturative stress, life satisfaction, social support, behavioral acculturation, behavioral enculturation, and coping self-efficacy were assessed. The results revealed that the variables of the model explained 16% of the variance in acculturative stress and 27% of the variance in life satisfaction. A final model, including the use of modification indices, provided good fit to the data. Findings also suggested that coping self-efficacy was a direct predictor of acculturative stress, and that behavioral acculturation and coping self-efficacy were direct predictors of students’ life satisfaction. Limitations, future research, and practical implications are discussed.

Architectural-Physical Co-Design of 3D CPUs with Micro-Fluidic Cooling

The performance, energy efficiency and cost improvements due to traditional technology scaling have begun to slow down and present diminishing returns. Underlying reasons for this trend include fundamental physical limits of transistor scaling, the growing significance of quantum effects as transistors shrink, and a growing mismatch between transistors and interconnects regarding size, speed and power. Continued Moore's Law scaling will not come from technology scaling alone, and must involve improvements to design tools and development of new disruptive technologies such as 3D integration. 3D integration presents potential improvements to interconnect power and delay by translating the routing problem into a third dimension, and facilitates transistor density scaling independent of technology node. Furthermore, 3D IC technology opens up a new architectural design space of heterogeneously-integrated high-bandwidth CPUs. Vertical integration promises to provide the CPU architectures of the future by integrating high performance processors with on-chip high-bandwidth memory systems and highly connected network-on-chip structures. Such techniques can overcome the well-known CPU performance bottlenecks referred to as memory and communication wall. However the promising improvements to performance and energy efficiency offered by 3D CPUs does not come without cost, both in the financial investments to develop the technology, and the increased complexity of design. Two main limitations to 3D IC technology have been heat removal and TSV reliability. Transistor stacking creates increases in power density, current density and thermal resistance in air cooled packages. Furthermore the technology introduces vertical through silicon vias (TSVs) that create new points of failure in the chip and require development of new BEOL technologies. Although these issues can be controlled to some extent using thermal-reliability aware physical and architectural 3D design techniques, high performance embedded cooling schemes, such as micro-fluidic (MF) cooling, are fundamentally necessary to unlock the true potential of 3D ICs. A new paradigm is being put forth which integrates the computational, electrical, physical, thermal and reliability views of a system. The unification of these diverse aspects of integrated circuits is called Co-Design. Independent design and optimization of each aspect leads to sub-optimal designs due to a lack of understanding of cross-domain interactions and their impacts on the feasibility region of the architectural design space. Co-Design enables optimization across layers with a multi-domain view and thus unlocks new high-performance and energy efficient configurations. Although the co-design paradigm is becoming increasingly necessary in all fields of IC design, it is even more critical in 3D ICs where, as we show, the inter-layer coupling and higher degree of connectivity between components exacerbates the interdependence between architectural parameters, physical design parameters and the multitude of metrics of interest to the designer (i.e. power, performance, temperature and reliability). In this dissertation we present a framework for multi-domain co-simulation and co-optimization of 3D CPU architectures with both air and MF cooling solutions. Finally we propose an approach for design space exploration and modeling within the new Co-Design paradigm, and discuss the possible avenues for improvement of this work in the future.

Nano-Engineering of Densely Packed Electrochemical Energy Storage Architectures by Atomic Layer Deposition

Nanostructures are highly attractive for future electrical energy storage devices because they enable large surface area and short ion transport time through thin electrode layers for high power devices. Significant enhancement in power density of batteries has been achieved by nano-engineered structures, particularly anode and cathode nanostructures spatially separated far apart by a porous membrane and/or a defined electrolyte region. A self-aligned nanostructured battery fully confined within a single nanopore presents a powerful platform to determine the rate performance and cyclability limits of nanostructured storage devices. Atomic layer deposition (ALD) has enabled us to create and evaluate such structures, comprised of nanotubular electrodes and electrolyte confined within anodic aluminum oxide (AAO) nanopores. The V2O5- V2O5 symmetric nanopore battery displays exceptional power-energy performance and cyclability when tested as a massively parallel device (~2billion/cm2), each with ~1m3 volume (~1fL). Cycled between 0.2V and 1.8V, this full cell has capacity retention of 95% at 5C rate and 46% at 150C, with more than 1000 charge/discharge cycles. These results demonstrate the promise of ultrasmall, self-aligned/regular, densely packed nanobattery structures as a testbed to study ionics and electrodics at the nanoscale with various geometrical modifications and as a building block for high performance energy storage systems[1, 2]. Further increase of full cell output potential is also demonstrated in asymmetric full cell configurations with various low voltage anode materials. The asymmetric full cell nanopore batteries, comprised of V2O5 as cathode and prelithiated SnO2 or anatase phase TiO2 as anode, with integrated nanotubular metal current collectors underneath each nanotubular storage electrode, also enabled by ALD. By controlling the amount of lithium ion prelithiated into SnO2 anode, we can tune full cell output voltage in the range of 0.3V and 3V. This asymmetric nanopore battery array displays exceptional rate performance and cyclability. When cycled between 1V and 3V, it has capacity retention of approximately 73% at 200C rate compared to 1C, with only 2% capacity loss after more than 500 charge/discharge cycles. With increased full cell output potential, the asymmetric V2O5-SnO2 nanopore battery shows significantly improved energy and power density. This configuration presents a more realistic test - through its asymmetric (vs symmetric) configuration – of performance and cyclability in nanoconfined environment. This dissertation covers (1) Ultra small electrochemical storage platform design and fabrication, (2) Electron and ion transport in nanostructured electrodes inside a half cell configuration, (3) Ion transport between anode and cathode in confined nanochannels in symmetric full cells, (4) Scale up energy and power density with geometry optimization and low voltage anode materials in asymmetric full cell configurations. As a supplement, selective growth of ALD to improve graphene conductance will also be discussed[3]. References: 1. Liu, C., et al., (Invited) A Rational Design for Batteries at Nanoscale by Atomic Layer Deposition. ECS Transactions, 2015. 69(7): p. 23-30. 2. Liu, C.Y., et al., An all-in-one nanopore battery array. Nature Nanotechnology, 2014. 9(12): p. 1031-1039. 3. Liu, C., et al., Improving Graphene Conductivity through Selective Atomic Layer Deposition. ECS Transactions, 2015. 69(7): p. 133-138.

Design of Nanophotonic Antireflection Coatings for III-V Thin-Film Photovoltaics

Thin-film photovoltaics have provided a critical design avenue to help decrease the overall cost of solar power. However, a major drawback of thin-film solar cell technology is decreased optical absorption, making compact, high-quality antireflection coatings of critical importance to ensure that all available light enters the cell. In this thesis, we describe high efficiency thin-film InP and GaAs solar cells that utilize a periodic array of nanocylinders as antireflection coatings. We use coupled optical and electrical simulations to find that these nanophotonic structures reduce the solar-weighted average reflectivity of InP and GaAs solar cells to around 1.3 %, outperforming the best double-layer antireflection coatings. The coupling between Mie scattering resonances and thin-film interference effects accurately describes the optical enhancement provided by the nanocylinders. The spectrally resolved reflectivity and J-V characteristics of the devices under AM1.5G solar illumination are determined via the coupled optical and electrical simulations, resulting in predicted power conversion efficiencies > 23 %. We conclude that the nanostructured coatings reduce reflection without negatively affecting the electronic properties of the InP and GaAs solar cells by separating the nanostructured optical components from the active layer of the device.