DEVELOPMENT OF LI+ AND NA+ CONDUCTING CERAMICS AND CERAMIC STRUCTURES FOR USE IN SOLID STATE BATTERIES

A solid state lithium metal battery based on a lithium garnet material was developed, constructed and tested. Specifically, a porous-dense-porous trilayer structure was fabricated by tape casting, a roll-to-roll technique conducive to high volume manufacturing. The high density and thin center layer (< 20 μm) effectively blocks dendrites even over hundreds of cycles. The microstructured porous layers, serving as electrode supports, are demonstrated to increase the interfacial surface area available to the electrodes and increase cathode loading. Reproducibility of flat, well sintered ceramics was achieved with consistent powderbed lattice parameter and ball milling of powderbed. Together, the resistance of the LLCZN trilayer was measured at an average of 7.6 ohm-cm2 in a symmetric lithium cell, significantly lower than any other reported literature results. Building on these results, a full cell with a lithium metal anode, LLCZN trilayer electrolyte, and LiCoO2 cathode was cycled 100 cycles without decay and an average ASR of 117 ohm-cm2. After cycling, the cell was held at open circuit for 24 hours without any voltage fade, demonstrating the absence of a dendrite or short-circuit of any type. Cost calculations guided the optimization of a trilayer structure predicted that resulting cells will be highly competitive in the marketplace as intrinsically safe lithium batteries with energy densities greater than 300 Wh/kg and 1000 Wh/L for under $100/kWh. Also in the pursuit of solid state batteries, an improved Na+ superionic conductor (NASICON) composition, Na3Zr2Si2PO12, was developed with a conductivity of 1.9x10-3 S/cm. New super-lithiated lithium garnet compositions, Li7.06La3Zr1.94Y0.06O12 and Li7.16La3Zr1.84Y0.16O12, were developed and studied revealing insights about the mechanisms of conductivity in lithium garnets.

Surface Insulation Resistance Degradation and Electrochemical Migration on Printed Circuit Boards

Widespread adoption of lead-free materials and processing for printed circuit board (PCB) assembly has raised reliability concerns regarding surface insulation resistance (SIR) degradation and electrochemical migration (ECM). As PCB conductor spacings decrease, electronic products become more susceptible to these failures mechanisms, especially in the presence of surface contamination and flux residues which might remain after no-clean processing. Moreover, the probability of failure due to SIR degradation and ECM is affected by the interaction between physical factors (such as temperature, relative humidity, electric field) and chemical factors (such as solder alloy, substrate material, no-clean processing). Current industry standards for assessing SIR reliability are designed to serve as short-term qualification tests, typically lasting 72 to 168 hours, and do not provide a prediction of reliability in long-term applications. The risk of electrochemical migration with lead-free assemblies has not been adequately investigated. Furthermore, the mechanism of electrochemical migration is not completely understood. For example, the role of path formation has not been discussed in previous studies. Another issue is that there are very few studies on development of rapid assessment methodologies for characterizing materials such as solder flux with respect to their potential for promoting ECM. In this dissertation, the following research accomplishments are described: 1). Long-term temp-humidity-bias (THB) testing over 8,000 hours assessing the reliability of printed circuit boards processed with a variety of lead-free solder pastes, solder pad finishes, and substrates. 2). Identification of silver migration from Sn3.5Ag and Sn3.0Ag0.5Cu lead-free solder, which is a completely new finding compared with previous research. 3). Established the role of path formation as a step in the ECM process, and provided clarification of the sequence of individual steps in the mechanism of ECM: path formation, electrodeposition, ion transport, electrodeposition, and filament formation. 4). Developed appropriate accelerated testing conditions for assessing the no-clean processed PCBs' susceptibility to ECM: a). Conductor spacings in test structures should be reduced in order to reflect the trend of higher density electronics and the effect of path formation, independent of electric field, on the time-to-failure. b). THB testing temperatures should be modified according to the material present on the PCB, since testing at 85oC can cause the evaporation of weak organic acids (WOAs) in the flux residues, leading one to underestimate the risk of ECM. 5). Correlated temp-humidity-bias testing with ion chromatography analysis and potentiostat measurement to develop an efficient and effective assessment methodology to characterize the effect of no-clean processing on ECM.