Large-Scale Controlled-Condition Experiment to Evaluate Light Weight Deflectometers for Modulus Determination and Compaction Quality Assurance of Unbound Pavement Materials

Compaction control using lightweight deflectometers (LWD) is currently being evaluated in several states and countries and fully implemented for pavement construction quality assurance (QA) by a few. Broader implementation has been hampered by the lack of a widely recognized standard for interpreting the load and deflection data obtained during construction QA testing. More specifically, reliable and practical procedures are required for relating these measurements to the fundamental material property—modulus—used in pavement design. This study presents a unique set of data and analyses for three different LWDs on a large-scale controlled-condition experiment. Three 4.5x4.5 m2 test pits were designed and constructed at target moisture and density conditions simulating acceptable and unacceptable construction quality. LWD testing was performed on the constructed layers along with static plate loading testing, conventional nuclear gauge moisture-density testing, and non-nuclear gravimetric and volumetric water content measurements. Additional material was collected for routine and exploratory tests in the laboratory. These included grain size distributions, soil classification, moisture-density relations, resilient modulus testing at optimum and field conditions, and an advanced experiment of LWD testing on top of the Proctor compaction mold. This unique large-scale controlled-condition experiment provides an excellent high quality resource of data that can be used by future researchers to find a rigorous, theoretically sound, and straightforward technique for standardizing LWD determination of modulus and construction QA for unbound pavement materials.

GEOTECHNICAL AND ENVIRONMENTAL IMPACTS OF STEEL SLAG IN EMBANKMENTS

Steel slag is a byproduct of iron and steel production by the metallurgical industries. Annually, 21 million tons of steel slag is produced in the United States. Most of the slag is landfilled, which represents a significant economic loss and a waste of valuable land space. Steel slag has great potential for the construction of highway embankments; however, its use has been limited due to its high swelling potential and alkalinity. The swelling potential of steel slags may lead to deterioration of the structural stability of highways, and high alkalinity poses an environmental challenge as it affects the leaching behavior of trace metals. This study seeks a methodology that promotes the use of steel slag in highway embankments by minimizing these two main disadvantages. Accelerated swelling tests were conducted to evaluate the swelling behavior of pure steel slag and water treatment residual (WTR) treated steel slag, where WTR is an alum-rich by-product of drinking water treatment plants. Sequential batch tests and column leach tests, as well as two different numerical analyses, UMDSurf and WiscLEACH, were carried out to check the environmental suitability of the methods. Tests were conducted to study the effect of a common borrow fill material that encapsulated the slag in the embankment and the effects of two subgrade soils on the chemical properties of slag leachate. The results indicated that an increase in WTR content in the steel slag-WTR mixtures yields a decrease in pH and most of the leached metal concentrations, except aluminum. The change in the levels of pH, after passing through encapsulation and subgrade, depends on the natural pHs of materials.

Machtverhältnisse und die Problematik des postkolonialen Blicks in Uwe Timms Morenga (1978) und Gerhard Seyfrieds Herero (2003)

Using a postcolonial methodology within a German Cultural Studies framework, this thesis applies a close reading to Uwe Timm’s 1978 novel Morenga and Gerhard Seyfried’s 2003 novel Herero. Both novels narrate the colonial experience in German Southwest Africa during the 1904-1907 Herero and Nama uprising through the eyes of a German male protagonist. I investigate how notions of the ‘other’ become ingrained in the collective cultural imaginary of a nation and manifest themselves as inherent truths used to justify methods of subjugation. I also examine the conflicts that arise due to the clash between these drastically different cultures in the “contact zone”, a term I borrow from Mary Louise Pratt. Emphasis is placed on analyzing the ways in which the natives’ use of mimicry allows for the creation of a cultural hybridity in which power relations are constantly negotiated and re-evaluated. I also problematize the difficulty both protagonists demonstrate in their quest to abandon the colonial gaze in favor of adopting a postcolonial perspective, an attempt that often appears ambivalent at best.

Physical Design Methodologies for Low Power and Reliable 3D ICs

As the semiconductor industry struggles to maintain its momentum down the path following the Moore's Law, three dimensional integrated circuit (3D IC) technology has emerged as a promising solution to achieve higher integration density, better performance, and lower power consumption. However, despite its significant improvement in electrical performance, 3D IC presents several serious physical design challenges. In this dissertation, we investigate physical design methodologies for 3D ICs with primary focus on two areas: low power 3D clock tree design, and reliability degradation modeling and management. Clock trees are essential parts for digital system which dissipate a large amount of power due to high capacitive loads. The majority of existing 3D clock tree designs focus on minimizing the total wire length, which produces sub-optimal results for power optimization. In this dissertation, we formulate a 3D clock tree design flow which directly optimizes for clock power. Besides, we also investigate the design methodology for clock gating a 3D clock tree, which uses shutdown gates to selectively turn off unnecessary clock activities. Different from the common assumption in 2D ICs that shutdown gates are cheap thus can be applied at every clock node, shutdown gates in 3D ICs introduce additional control TSVs, which compete with clock TSVs for placement resources. We explore the design methodologies to produce the optimal allocation and placement for clock and control TSVs so that the clock power is minimized. We show that the proposed synthesis flow saves significant clock power while accounting for available TSV placement area. Vertical integration also brings new reliability challenges including TSV's electromigration (EM) and several other reliability loss mechanisms caused by TSV-induced stress. These reliability loss models involve complex inter-dependencies between electrical and thermal conditions, which have not been investigated in the past. In this dissertation we set up an electrical/thermal/reliability co-simulation framework to capture the transient of reliability loss in 3D ICs. We further derive and validate an analytical reliability objective function that can be integrated into the 3D placement design flow. The reliability aware placement scheme enables co-design and co-optimization of both the electrical and reliability property, thus improves both the circuit's performance and its lifetime. Our electrical/reliability co-design scheme avoids unnecessary design cycles or application of ad-hoc fixes that lead to sub-optimal performance. Vertical integration also enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. In addition, a dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance. The proposed physical design methodologies should act as important building blocks for 3D ICs and push 3D ICs toward mainstream acceptance in the near future.