EXPERIMENTAL DEMONSTRATION OF LIGHT TRAPPING AND INTERNAL LIGHT SCATTERING IN SOLAR CELLS

Renewable energy technologies have long-term economic and environmental advantages over fossil fuels, and solar power is the most abundant renewable resource, supplying 120 PW over earth’s surface. In recent years the cost of photovoltaic modules has reached grid parity in many areas of the world, including much of the USA. A combination of economic and environmental factors has encouraged the adoption of solar technology and led to an annual growth rate in photovoltaic capacity of 76% in the US between 2010 and 2014. Despite the enormous growth of the solar energy industry, commercial unit efficiencies are still far below their theoretical limits. A push for thinner cells may reduce device cost and could potentially increase device performance. Fabricating thinner cells reduces bulk recombination, but at the cost of absorbing less light. This tradeoff generally benefits thinner devices due to reduced recombination. The effect continues up to a maximum efficiency where the benefit of reduced recombination is overwhelmed by the suppressed absorption. Light trapping allows the solar cell to circumvent this limitation and realize further performance gains (as well as continue cost reduction) from decreasing the device thickness. This thesis presents several advances in experimental characterization, theoretical modeling, and device applications for light trapping in thin-film solar cells. We begin by introducing light trapping strategies and discuss theoretical limits of light trapping in solar cells. This is followed by an overview of the equipment developed for light trapping characterization. Next we discuss our recent work measuring internal light scattering and a new model of scattering to predict the effects of dielectric nanoparticle back scatterers on thin-film device absorption. The new model is extended and generalized to arbitrary stacks of stratified media containing scattering structures. Finally, we investigate an application of these techniques using polymer dispersed liquid crystals to produce switchable solar windows. We show that these devices have the potential for self-powering.

Combined heat and power and campus carbon footprint reduction

Gemstone Team Cogeneration Technology

Degenerate mixtures of rubidium and ytterbium for engineering open quantum systems

In the last two decades, experimental progress in controlling cold atoms and ions now allows us to manipulate fragile quantum systems with an unprecedented degree of precision. This has been made possible by the ability to isolate small ensembles of atoms and ions from noisy environments, creating truly closed quantum systems which decouple from dissipative channels. However in recent years, several proposals have considered the possibility of harnessing dissipation in open systems, not only to cool degenerate gases to currently unattainable temperatures, but also to engineer a variety of interesting many-body states. This thesis will describe progress made towards building a degenerate gas apparatus that will soon be capable of realizing these proposals. An ultracold gas of ytterbium atoms, trapped by a species-selective lattice will be immersed into a Bose-Einstein condensate (BEC) of rubidium atoms which will act as a bath. Here we describe the challenges encountered in making a degenerate mixture of rubidium and ytterbium atoms and present two experiments performed on the path to creating a controllable open quantum system. The first experiment will describe the measurement of a tune-out wavelength where the light shift of $\Rb{87}$ vanishes. This wavelength was used to create a species-selective trap for ytterbium atoms. Furthermore, the measurement of this wavelength allowed us to extract the dipole matrix element of the $5s \rightarrow 6p$ transition in $\Rb{87}$ with an extraordinary degree of precision. Our method to extract matrix elements has found use in atomic clocks where precise knowledge of transition strengths is necessary to account for minute blackbody radiation shifts. The second experiment will present the first realization of a degenerate Bose-Fermi mixture of rubidium and ytterbium atoms. Using a three-color optical dipole trap (ODT), we were able to create a highly-tunable, species-selective potential for rubidium and ytterbium atoms which allowed us to use $\Rb{87}$ to sympathetically cool $\Yb{171}$ to degeneracy with minimal loss. This mixture is the first milestone creating the lattice-bath system and will soon be used to implement novel cooling schemes and explore the rich physics of dissipation.

Physical Design Methodologies for Low Power and Reliable 3D ICs

As the semiconductor industry struggles to maintain its momentum down the path following the Moore's Law, three dimensional integrated circuit (3D IC) technology has emerged as a promising solution to achieve higher integration density, better performance, and lower power consumption. However, despite its significant improvement in electrical performance, 3D IC presents several serious physical design challenges. In this dissertation, we investigate physical design methodologies for 3D ICs with primary focus on two areas: low power 3D clock tree design, and reliability degradation modeling and management. Clock trees are essential parts for digital system which dissipate a large amount of power due to high capacitive loads. The majority of existing 3D clock tree designs focus on minimizing the total wire length, which produces sub-optimal results for power optimization. In this dissertation, we formulate a 3D clock tree design flow which directly optimizes for clock power. Besides, we also investigate the design methodology for clock gating a 3D clock tree, which uses shutdown gates to selectively turn off unnecessary clock activities. Different from the common assumption in 2D ICs that shutdown gates are cheap thus can be applied at every clock node, shutdown gates in 3D ICs introduce additional control TSVs, which compete with clock TSVs for placement resources. We explore the design methodologies to produce the optimal allocation and placement for clock and control TSVs so that the clock power is minimized. We show that the proposed synthesis flow saves significant clock power while accounting for available TSV placement area. Vertical integration also brings new reliability challenges including TSV's electromigration (EM) and several other reliability loss mechanisms caused by TSV-induced stress. These reliability loss models involve complex inter-dependencies between electrical and thermal conditions, which have not been investigated in the past. In this dissertation we set up an electrical/thermal/reliability co-simulation framework to capture the transient of reliability loss in 3D ICs. We further derive and validate an analytical reliability objective function that can be integrated into the 3D placement design flow. The reliability aware placement scheme enables co-design and co-optimization of both the electrical and reliability property, thus improves both the circuit's performance and its lifetime. Our electrical/reliability co-design scheme avoids unnecessary design cycles or application of ad-hoc fixes that lead to sub-optimal performance. Vertical integration also enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. In addition, a dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance. The proposed physical design methodologies should act as important building blocks for 3D ICs and push 3D ICs toward mainstream acceptance in the near future.