Hybrid integration and packaging of grating-coupled silicon photonics

This thesis covers both the packaging of silicon photonic devices with fiber inputs and outputs as well as the integration of laser light sources with these same devices. The principal challenge in both of these pursuits is coupling light into the submicrometer waveguides that are the hallmark of silicon-on-insulator (SOI) systems. Previous work on grating couplers is leveraged to design new approaches to bridge the gap between the highly-integrated domain of silicon, the Interconnected world of fiber and the active region of III-V materials. First, a novel process for the planar packaging of grating couplers with fibers is explored in detail. This technology allows the creation of easy-to-use test platforms for laser integration and also stands on its own merits as an enabling technology for next-generation silicon photonics systems. The alignment tolerances of this process are shown to be well-suited to a passive alignment process and for wafer-scale assembly. Furthermore, this technology has already been used to package demonstrators for research partners and is included in the offerings of the ePIXfab silicon photonics foundry and as a design kit for PhoeniX Software’s MaskEngineer product. After this, a process for hybridly integrating a discrete edge-emitting laser with a silicon photonic circuit using near-vertical coupling is developed and characterized. The details of the various steps of the design process are given, including mechanical, thermal, optical and electrical steps. The interrelation of these design domains is also discussed. The construction process for a demonstrator is outlined, and measurements are presented of a series of single-wavelength Fabry-Pérot lasers along with a two-section laser tunable in the telecommunications C-band. The suitability and potential of this technology for mass manufacture is demonstrated, with further opportunities for improvement detailed and discussed in the conclusion.

Novel processes, test structures and characterisation for future germanium technologies

In order to widely use Ge and III-V materials instead of Si in advanced CMOS technology, the process and integration of these materials has to be well established so that their high mobility benefit is not swamped by imperfect manufacturing procedures. In this dissertation number of key bottlenecks in realization of Ge devices are investigated; We address the challenge of the formation of low resistivity contacts on n-type Ge, comparing conventional and advanced rapid thermal annealing (RTA) and laser thermal annealing (LTA) techniques respectively. LTA appears to be a feasible approach for realization of low resistivity contacts with an incredibly sharp germanide-substrate interface and contact resistivity in the order of 10 -7 Ω.cm2. Furthermore the influence of RTA and LTA on dopant activation and leakage current suppression in n+/p Ge junction were compared. Providing very high active carrier concentration > 1020 cm-3, LTA resulted in higher leakage current compared to RTA which provided lower carrier concentration ~1019 cm-3. This is an indication of a trade-off between high activation level and junction leakage current. High ION/IOFF ratio ~ 107 was obtained, which to the best of our knowledge is the best reported value for n-type Ge so far. Simulations were carried out to investigate how target sputtering, dose retention, and damage formation is generated in thin-body semiconductors by means of energetic ion impacts and how they are dependent on the target physical material properties. Solid phase epitaxy studies in wide and thin Ge fins confirmed the formation of twin boundary defects and random nucleation growth, like in Si, but here 600 °C annealing temperature was found to be effective to reduce these defects. Finally, a non-destructive doping technique was successfully implemented to dope Ge nanowires, where nanowire resistivity was reduced by 5 orders of magnitude using PH3 based in-diffusion process.