Atomic layer deposition of interface control layers for the fabrication of III/V MOS devices

The continued advancement of metal oxide semiconductor field effect transistor (MOSFET) technology has shifted the focus from Si/SiO2 transistors towards high-κ/III-V transistors for high performance, faster devices. This has been necessary due to the limitations associated with the scaling of the SiO2 thickness below ~1 nm and the associated increased leakage current due to direct electron tunnelling through the gate oxide. The use of these materials exhibiting lower effective charge carrier mass in conjunction with the use of a high-κ gate oxide allows for the continuation of device scaling and increases in the associated MOSFET device performance. The high-κ/III-V interface is a critical challenge to the integration of high-κ dielectrics on III-V channels. The interfacial chemistry of the high-κ/III-V system is more complex than Si, due to the nature of the multitude of potential native oxide chemistries at the surface with the resultant interfacial layer showing poor electrical insulating properties when high-κ dielectrics are deposited directly on these oxides. It is necessary to ensure that a good quality interface is formed in order to reduce leakage and interface state defect density to maximise channel mobility and reduce variability and power dissipation. In this work, the ALD growth of aluminium oxide (Al2O3) and hafnium oxide (HfO2) after various surface pre-treatments was carried out, with the aim of improving the high-κ/III-V interface by reducing the Dit – the density of interface defects caused by imperfections such as dangling bonds, dimers and other unsatisfied bonds at the interfaces of materials. A brief investigation was performed into the structural and electrical properties of Al2O3 films deposited on In0.53Ga0.47As at 200 and 300oC via a novel amidinate precursor. Samples were determined to experience a severe nucleation delay when deposited directly on native oxides, leading to diminished functionality as a gate insulator due to largely reduced growth per cycle. Aluminium oxide MOS capacitors were prepared by ALD and the electrical characteristics of GaAs, In0.53Ga0.47As and InP capacitors which had been exposed to pre-pulse treatments from triethyl gallium and trimethyl indium were examined, to determine if self-cleaning reactions similar to those of trimethyl aluminium occur for other alkyl precursors. An improved C-V characteristic was observed for GaAs devices indicating an improved interface possibly indicating an improvement of the surface upon pre-pulsing with TEG, conversely degraded electrical characteristics observed for In0.53Ga0.47As and InP MOS devices after pre-treatment with triethyl gallium and trimethyl indium respectively. The electrical characteristics of Al2O3/In0.53Ga0.47As MOS capacitors after in-situ H2/Ar plasma treatment or in-situ ammonium sulphide passivation were investigated and estimates of interface Dit calculated. The use of plasma reduced the amount of interface defects as evidenced in the improved C-V characteristics. Samples treated with ammonium sulphide in the ALD chamber were found to display no significant improvement of the high-κ/III-V interface. HfO2 MOS capacitors were fabricated using two different precursors comparing the industry standard hafnium chloride process with deposition from amide precursors incorporating a ~1nm interface control layer of aluminium oxide and the structural and electrical properties investigated. Capacitors furnished from the chloride process exhibited lower hysteresis and improved C-V characteristics as compared to that of hafnium dioxide grown from an amide precursor, an indication that no etching of the film takes place using the chloride precursor in conjunction with a 1nm interlayer. Optimisation of the amide process was carried out and scaled samples electrically characterised in order to determine if reduced bilayer structures display improved electrical characteristics. Samples were determined to exhibit good electrical characteristics with a low midgap Dit indicative of an unpinned Fermi level

AuxAg1-x alloy seeds: A way to control growth, morphology and defect formation in Ge nanowires

Germanium (Ge) nanowires are of current research interest for high speed nanoelectronic devices due to the lower band gap and high carrier mobility compatible with high K-dielectrics and larger excitonic Bohr radius ensuing a more pronounced quantum confinement effect [1-6]. A general way for the growth of Ge nanowires is to use liquid or a solid growth promoters in a bottom-up approach which allow control of the aspect ratio, diameter, and structure of 1D crystals via external parameters, such as precursor feedstock, temperature, operating pressure, precursor flow rate etc [3, 7-11]. The Solid-phase seeding is preferred for more control processing of the nanomaterials and potential suppression of the unintentional incorporation of high dopant concentrations in semiconductor nanowires and unrequired compositional tailing of the seed-nanowire interface [2, 5, 9, 12]. There are therefore distinct features of the solid phase seeding mechanism that potentially offer opportunities for the controlled processing of nanomaterials with new physical properties. A superior control over the growth kinetics of nanowires could be achieved by controlling the inherent growth constraints instead of external parameters which always account for instrumental inaccuracy. The high dopant concentrations in semiconductor nanowires can result from unintentional incorporation of atoms from the metal seed material, as described for the Al catalyzed VLS growth of Si nanowires [13] which can in turn be depressed by solid-phase seeding. In addition, the creation of very sharp interfaces between group IV semiconductor segments has been achieved by solid seeds [14], whereas the traditionally used liquid Au particles often leads to compositional tailing of the interface [15] . Korgel et al. also described the superior size retention of metal seeds in a SFSS nanowire growth process, when compared to a SFLS process using Au colloids [12]. Here in this work we have used silver and alloy seed particle with different compositions to manipulate the growth of nanowires in sub-eutectic regime. The solid seeding approach also gives an opportunity to influence the crystallinity of the nanowires independent of the substrate. Taking advantage of the readily formation of stacking faults in metal nanoparticles, lamellar twins in nanowires could be formed.