Age, job characteristics and coronary health

Background: Workplace demographics are changing in many European countries with a higher proportion of older workers in employment. Research has shown that there is an association between job strain and cardiovascular disease, but this relationship is unclear for the older worker. Aims: To investigate the association between job strain and a coronary event comparing younger and older male workers. Methods: Cases with a first-time coronary event were recruited from four coronary/intensive care units (1999-2001). Matched controls were recruited from the case's general practitioner surgery. Physical measurements were taken and self-administered questionnaires completed with questions on job characteristics, job demands and control. Unconditional logistic regression was carried out adjusting for classical cardiovascular risk factors. Results: There were 227 cases and 277 matched controls. Age stratified analyses showed a clear difference between younger (= 50 years) workers with regard to the exposure of job strain (job demands and control) and the association between these factors and cardiovascular disease. Older workers who had a coronary event were four times as likely to have high job strain [OR = 4.09 (1.29-13.02)] and more likely to report low job control [ OR = 0.83 (0.72-0.95)]. Conclusions: Job control emerged as a potential protective factor for heart disease and this evidence was stronger in the older male worker. Nevertheless, they were significantly more likely to have job strain. These results suggest that older workers may be more susceptible to job strain.

Average-case analysis of power consumption in embedded systems

Power efficiency is one of the most important constraints in the design of embedded systems since such systems are generally driven by batteries with limited energy budget or restricted power supply. In every embedded system, there are one or more processor cores to run the software and interact with the other hardware components of the system. The power consumption of the processor core(s) has an important impact on the total power dissipated in the system. Hence, the processor power optimization is crucial in satisfying the power consumption constraints, and developing low-power embedded systems. A key aspect of research in processor power optimization and management is “power estimation”. Having a fast and accurate method for processor power estimation at design time helps the designer to explore a large space of design possibilities, to make the optimal choices for developing a power efficient processor. Likewise, understanding the processor power dissipation behaviour of a specific software/application is the key for choosing appropriate algorithms in order to write power efficient software. Simulation-based methods for measuring the processor power achieve very high accuracy, but are available only late in the design process, and are often quite slow. Therefore, the need has arisen for faster, higher-level power prediction methods that allow the system designer to explore many alternatives for developing powerefficient hardware and software. The aim of this thesis is to present fast and high-level power models for the prediction of processor power consumption. Power predictability in this work is achieved in two ways: first, using a design method to develop power predictable circuits; second, analysing the power of the functions in the code which repeat during execution, then building the power model based on average number of repetitions. In the first case, a design method called Asynchronous Charge Sharing Logic (ACSL) is used to implement the Arithmetic Logic Unit (ALU) for the 8051 microcontroller. The ACSL circuits are power predictable due to the independency of their power consumption to the input data. Based on this property, a fast prediction method is presented to estimate the power of ALU by analysing the software program, and extracting the number of ALU-related instructions. This method achieves less than 1% error in power estimation and more than 100 times speedup in comparison to conventional simulation-based methods. In the second case, an average-case processor energy model is developed for the Insertion sort algorithm based on the number of comparisons that take place in the execution of the algorithm. The average number of comparisons is calculated using a high level methodology called MOdular Quantitative Analysis (MOQA). The parameters of the energy model are measured for the LEON3 processor core, but the model is general and can be used for any processor. The model has been validated through the power measurement experiments, and offers high accuracy and orders of magnitude speedup over the simulation-based method.