The geographies of encounter: investigating the spatiality and construction of 'meaningful' encounters with difference through the experiences of international students at University College Cork, Ireland

The purpose of this research is to investigate how international students negotiate encounters with Irish students and construct ‘meaning’ from those encounters in the spaces of the university and city. As cities are increasingly characterised by a multiplexity of diversity, the issue of living with difference is becoming more and more pertinent. In the wake of escalating socio-spatial polarisation, inter-cultural tension, racism, and xenophobia, the geographies of encounter seek to untangle the interactions that occur in the quotidian activities and spaces of everyday life to determine whether such encounters might reduce prejudice, antipathy and indifference and establish common social bonds (Amin 2002; Valentine 2008). Thus far, the literature has investigated a number of sites of encounter; public space, the home, neighbourhoods, schools, sports clubs, public transport, cafes and libraries (Wilson 2011; Schuermans 2013; Hemming 2011; Neal and Vincent 2011; Mayblin, Valentine and Anderrson 2015; Laurier and Philo 2006; Valentine and Sadgrove 2013; Harris, Valentine and Piekut 2014; Fincher and Iveson 2008). While these spaces produce a range of outcomes, the literature remains frustrated by a lack of clarity of what constitutes a ‘meaningful’ encounter and how such encounters might be planned for. Drawing on survey and interview data with full-time international students at University College Cork, Ireland, this study contributes to understanding how encounters are shaped by the construction and reproduction of particular identities in particular spaces, imbuing spaces with uneven power frameworks that produce diverse outcomes. Rather than identifying a singular ‘meaningful’ outcome of encounter as a potential panacea to the issues of exclusion and oppression, the contention here is to recognise a range of outcomes that are created by individuals in a range of ways. To define one outcome of encounter as ‘meaningful’ is to overlook the scale of intensity of diverse interactions and the multiplicity of ways in which people learn to live with difference.

Systematic delay-driven power optimisation and power-driven delay optimisation of combinational circuits

With the proliferation of mobile wireless communication and embedded systems, the energy efficiency becomes a major design constraint. The dissipated energy is often referred as the product of power dissipation and the input-output delay. Most of electronic design automation techniques focus on optimising only one of these parameters either power or delay. Industry standard design flows integrate systematic methods of optimising either area or timing while for power consumption optimisation one often employs heuristics which are characteristic to a specific design. In this work we answer three questions in our quest to provide a systematic approach to joint power and delay Optimisation. The first question of our research is: How to build a design flow which incorporates academic and industry standard design flows for power optimisation? To address this question, we use a reference design flow provided by Synopsys and integrate in this flow academic tools and methodologies. The proposed design flow is used as a platform for analysing some novel algorithms and methodologies for optimisation in the context of digital circuits. The second question we answer is: Is possible to apply a systematic approach for power optimisation in the context of combinational digital circuits? The starting point is a selection of a suitable data structure which can easily incorporate information about delay, power, area and which then allows optimisation algorithms to be applied. In particular we address the implications of a systematic power optimisation methodologies and the potential degradation of other (often conflicting) parameters such as area or the delay of implementation. Finally, the third question which this thesis attempts to answer is: Is there a systematic approach for multi-objective optimisation of delay and power? A delay-driven power and power-driven delay optimisation is proposed in order to have balanced delay and power values. This implies that each power optimisation step is not only constrained by the decrease in power but also the increase in delay. Similarly, each delay optimisation step is not only governed with the decrease in delay but also the increase in power. The goal is to obtain multi-objective optimisation of digital circuits where the two conflicting objectives are power and delay. The logic synthesis and optimisation methodology is based on AND-Inverter Graphs (AIGs) which represent the functionality of the circuit. The switching activities and arrival times of circuit nodes are annotated onto an AND-Inverter Graph under the zero and a non-zero-delay model. We introduce then several reordering rules which are applied on the AIG nodes to minimise switching power or longest path delay of the circuit at the pre-technology mapping level. The academic Electronic Design Automation (EDA) tool ABC is used for the manipulation of AND-Inverter Graphs. We have implemented various combinatorial optimisation algorithms often used in Electronic Design Automation such as Simulated Annealing and Uniform Cost Search Algorithm. Simulated Annealing (SMA) is a probabilistic meta heuristic for the global optimization problem of locating a good approximation to the global optimum of a given function in a large search space. We used SMA to probabilistically decide between moving from one optimised solution to another such that the dynamic power is optimised under given delay constraints and the delay is optimised under given power constraints. A good approximation to the global optimum solution of energy constraint is obtained. Uniform Cost Search (UCS) is a tree search algorithm used for traversing or searching a weighted tree, tree structure, or graph. We have used Uniform Cost Search Algorithm to search within the AIG network, a specific AIG node order for the reordering rules application. After the reordering rules application, the AIG network is mapped to an AIG netlist using specific library cells. Our approach combines network re-structuring, AIG nodes reordering, dynamic power and longest path delay estimation and optimisation and finally technology mapping to an AIG netlist. A set of MCNC Benchmark circuits and large combinational circuits up to 100,000 gates have been used to validate our methodology. Comparisons for power and delay optimisation are made with the best synthesis scripts used in ABC. Reduction of 23% in power and 15% in delay with minimal overhead is achieved, compared to the best known ABC results. Also, our approach is also implemented on a number of processors with combinational and sequential components and significant savings are achieved.